Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Manufacturing/Packaging

NEC says 55nm process cuts power consumption

Posted: 07 Dec 2005 ?? ?Print Version ?Bookmark and Share

Keywords:NEC Electronics? 55nm? UX7LS? emersion lithography?

Japan-based NEC Electronics Corp. announced early this week (Dec. 5) that it has developed a 55nm node process named UX7LS that will employ emersion lithography and higher dielectric constant (high-k) material. The company claims the process provides one-tenth lower power consumption in both operating and standby modes, than 65nm processes.

"UX7LS is an improved version of the 65-nm process. By combining with the 65nm process technology with high-k film, we've developed the ultimate low power LSI," said Takaaki Kuwata, GM of advanced device development division of the company. "The process will be applicable to LSIs for products from mobile phones, mobile consumer products to network systems," he said.

NEC Electronics had disclosed a 65nm process named UX7, which employs conventional dry lithography and a transistor structure without high-k technology. Engineering samples of both high speed and low power versions will be available by the middle of next year.

"Just by scaling down to 55nm, the power consumption can not be lowered," said Kuwata. "Our Ultimate Low Power technology, including the Vdd (source voltage)/Vth (threshold voltage) control and high-k technology realized low power consumption."

The NEC Electronics team used the combination of body-bias sensitive device structure to control transistor threshold voltage and high-k (HfSiON) gate insulating film to realize the low power devices. The High-k gate insulator film is grown on the conventional SiO2 layer at the gate. The high-k insulator layer is equal to 1.8nm thick SiO2 layer.

"We can supply the highest density and smallest SRAM around 2007 to 2008, which will be the most advanced device until the 45nm node products become available on the market," said Kuwata. The SRAM on the UX7LS process will have a gate density of 925,000 gates per square meter and cell size of 0.432 square microns.

The company intends to offer samples in summer 2007 and begin volume production within the year.

It is an advantage that most 65-nm production facilities can be used for the 55nm process, said Kuwata. Only for critical processes will they use the emersion lithography system. ASML will supply the emersion lithography system for sample fabrication and pilot production. The volume production system has not yet been decided, according to Kuwata. The first metal layer will have a 180nm pitch.

NEC Electronics announced the joint development agreement with Toshiba for the 45nm node and beyond technologies. The UX7LS technology will eventually be merged into the jointly developed process, tentatively designated UX8.

Based on the joint 45nm process, NEC Electronics will continue developing differentiated technologies such as embedded DRAM independent from its partner, according to Kuwata.

- Yoshiko Hara
EE Times

Article Comments - NEC says 55nm process cuts power con...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top