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P.A. Semi's 65nm processor developed with Cadence platform

Posted: 07 Dec 2005 ?? ?Print Version ?Bookmark and Share

Keywords:Cadence Design Systems? Encounter digital IC design platform? P.A. Semi? 65nm? PWRficient processor?

Cadence Design Systems Inc. announced that its Cadence Encounter digital IC design platform has helped P.A. Semi develop its new 65nm multicore PWRficient processor with a successful test-chip tapeout in March 2005. P.A. Semi's first PWRficient processor, a dual-core device operating at 2GHz with 5W to 13W power dissipation, is being developed from the ground up using the complete Encounter solution from RTL synthesis to GDSII. Silicon samples of the test chip are running at 2GHz.

To achieve the power, frequency and density targets for the design, said the press release, P.A. Semi tapped the strength of a complete SoC Encounter XL-based flow. This RTL-to-GDSII system includes RTL global synthesis, prototyping, placement, optimization and routing. The platform's advanced capabilities in multi-objective low-power synthesis, global physical synthesis, clock-tree synthesis, manufacturing-aware extraction, and signal integrity and power analysis specifically address the complex issues of 65nm design, added Cadence.

"The Cadence Encounter platform helped us achieve our test-chip tapeout and is assisting us in keeping our processor tapeout on schedule," said Sribalan Santhanam, VP of engineering, Design Group, at P.A. Semi. "The SoC Encounter XL RTL to GDSII system's advanced capabilities in RTL global synthesis, floorplanning, global physical synthesis and routing helps our designs to meet the required performance specifications and the NanoRoute nanometer router's ability to support 65nm rules is unprecedented."

Based on the IBM Power Architecture, the scalable, power-efficient PWRficient platform-processor family targets the high-performance embedded and computing markets.

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