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Japanese researchers unveil 3-D stack for chip integration

Posted: 08 Dec 2005 ?? ?Print Version ?Bookmark and Share

Keywords:three-dimensional? 3-d? integration technology? Super-Smart-Stack?

Japanese researchers have come up with a new three-dimensional integration technology called Super-Smart-Stack that uses a self-assembly technique to maintain chip alignment accuracy to within 1?m.

The details of the process, delivered at the International Electron Devices Meeting (IEDM) early this week (Dec. 6), portends the use of the self-assembly technique to stack various chips types with different sizes and thicknesses. Most are fabricated using different process technologies.

In order to dramatically improve the overall yield for 3-D chips, it is preferable to stack known-good dice (KGDs) as opposed to chip on chip. Researchers at Tohoku University in Japan proposed vertically stacked KGDs in a batch, where many KGDs are temporarily glued to a wafer using the self-assembly technique. Wafers are then stacked with many KGDs.

The researchers claimed the technique represents the ultimate integration technology. Super-Smart-Stack also involves a ten-step process in which KGDs from the first layer of 3D chips are aligned and bonded on the wafer via self-assembly. The chip wafer also acts as a thick supporting wafer. KGDs for the second layer are aligned and temporarily glued to a thick handling wafer.

The KGDs are then temporarily glued to the handling wafer that is bonded to dice on the supporting wafer, thereby eliminating wafer handling.

By repeating the sequence, a three-dimensional chip is created. The resulting super chip includes various thin chips with different sizesall vertically stacked.

A 3-D SRAM test chip with ten memory layers has been fabricated using the Super-Smart-Stack technology, the researchers reported at IEDM.

- Nicolas Mokhoff
EE Times

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