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IEEE approves SystemC standard

Posted: 14 Dec 2005 ?? ?Print Version ?Bookmark and Share

Keywords:IEEE? SystemC? electronic design language standard? EDA?

In a move widely applauded within the design community, IEEE said early this week (Dec. 12) it has approved the SystemC electronic design language standard. IEEE standardization may help bring SystemC into more widespread use and pave the way for further support from commercial EDA tools.

SystemC, or IEEE 1666, was approved based on the SystemC 2.1 Language Reference Manual developed by Open SystemC Initiative (OSCI) and delivered to IEEE in June.

According to IEEE, SystemC 2.1 broadens hardware and software modeling capabilities to higher levels of abstraction. It lets engineers architect entire systems from the start, which speeds design, and allows for the sharing and reuse of intellectual property (IP), IEEE said.

According to Alain Clouard, OSCI chairman, the standardization process was accelerated by the reference manual. In a statement issued by IEEE Monday, Chuck Adams, chair of the IEEE Standards Association Corporate Advisory Group, thanked OSCI for the "outstanding technical contributions" and called the rapid achievement of the standardit took less than eight months for approvala "significant achievement."

Clouard said OSCI would continue to work to add to SystemC with add-on layers, such as the transaction-level modeling standard the organization released in June.

In addition to spanning design and verification from concept to implementation in hardware and software, IEEE said, SystemC 2.1 provides an interoperable modeling platform for developing and exchanging fast system-level C++ models. It also forms a bridge between architectural design and register-transfer level (RTL) implementation, providing a platform for the creation of interoperable tools in a rich design environment, the organization said.

"Our company has been addressing the complexity of system-on-chip (SoC) using the SystemC language for the last four years," said Jean-Marc Chateau, director of IP and design at STMicroelectronics, an OSCI member company, in a statement. "Winning the time to volume challenge is our key objective and we are moving our environment to use the IEEE 1666 standard. We expect our suppliers and partners to deliver system IP models based on this standard."

Victor Berman, chair of the P1666 Working Group at IEEE and director of language standards at Cadence Design Systems Inc., said in a separate statement that the SystemC standard helps to address the sheer complexity of today's SoCs and the significant rise in the demand for IP reuse.

"The standard arms engineers with a powerful integrated platform to tackle design, simulation, verification and architectural modeling challenges," Berman said.

Clouard said, from his experience, he thinks that it is now very clear that SystemC and SystemVerilog are being used together in a complimentary way, with designers using SystemC to design the main specifications and System Verilog being used by designers of the system-level hardware.

SystemVerilog was approved as an IEEE standard in November.

- Dylan McGrath
EE Times

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