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Mixed-signal FPGA opens new horizons

Posted: 15 Dec 2005 ?? ?Print Version ?Bookmark and Share

Keywords:Actel? Fusion? Programmable System Chip? PSC? mixed-signal FPGA?

Going boldly where no programmable logic has gone before, Actel Corp. is slated to unwrap this week its Fusion Programmable System Chip (PSC), said to be the world's first mixed-signal FPGA family.

The Fusion PSC integrates configurable analog blocks, flash memory, clock generation and management, and digital logic into one monolithic device. Actel believes the device will open new applications for FPGAs, including power and temperature management, motor and motion control, system initialization and configuration, program and data storage, and "live at power-up" clock generation, conditioning and distribution.

"We see this as a game changer in the FPGA space," said Dennis Kish, VP of marketing at Actel. "We've never had anything remotely like it in terms of customer reaction."

Actel offered a sneak preview of the Fusion architecture last summer, and this week plans to announce the device's availability, along with far more details about its components. Actel will also roll out the Libero 7.0 integrated development environment (IDE), upgraded to support the Fusion PSC and allow the configuration of its analog blocks.

The Fusion PSC will include an A/D converter, analog inputs, integrated oscillators and embedded flash memory. As such, said Martin Mason, director of silicon product marketing at Actel, the Fusion will integrate much of the "analog confetti" that is typically spread across printed-circuit boards, which enables systems to be smaller, more reliable and lower-power.

As an FPGA, the Fusion will also offer far lower design costs than mixed-signal ASICsbut it doesn't match their performance or capacity. With prices starting around $5 in quantity, it would also generally be costlier for very high volumes.

The highest-capacity member in the initial Fusion family, the AFS1500, offers 1.5 million system gates, roughly equivalent to 150,000 ASIC logic gates. The low-capacity AFS090 offers 90,000 system gates. The devices run at speeds of up to 350MHz and are primarily aimed at applications in the 100MHz to 200MHz range.

"There will be applications whose performance requirements we cannot meet, but we are just beginning down this road and over time, we will address as much of the market space as we can with this technology," said Mason. "Our initial offering is a very good, general-purpose mixed-signal solution with power management and analog front-end manipulation."

The analog circuitry in the Fusion, it should be noted, is configurable but not programmable. "The analog itself is fixed," said Mason. "It's not like we're hooking together transistors. We have predefined and very efficient analog blocks inside the system, and you control those with register settings that get preloaded from flash memory at system startup."

Unique attributes
While there have been small attempts in the past at adding some analog capabilities to FPGAs, the Fusion offers many features that have never been seen on an FPGA before, according to Mason. Among these is an analog-to-digital converter (ADC) with frequencies up to 600kilosamples/second and resolution up to 12 bits.

The ADC is used primarily for digitizing signals that come from analog "quads," which are analog I/Os that support connections from -12V to 12V. A configurable 32-channel analog multiplexer, which Mason said is unique in an FPGA fabric, sits between the quads and the ADC.

- Richard Goering
EE Times

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