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Bridging chip upgrades bus interface designs to PCI Express

Posted: 15 Dec 2005 ?? ?Print Version ?Bookmark and Share

Keywords:PLX Technology? bridge chip? PEX 8311? DSP? FPGA?

PLX Technology Inc.'s latest bridge chip dubbed the PEX 8311 is designed to upgrade standard processor, DSP and FPGA bus interface designs to PCI Express (PCIe).

The PEX 8311 1-lane PCIe to 32-bit, 66MHz generic local bus bridge offers protocol translations between these two standards. With the PEX 8311, designers of communication line cards, surveillance systems, industrial control, IP media server and medical imaging systems can add scalable high-bandwidth interconnection. PCI-based embedded system designs that are either root complex or endpoint based can migrate to PCIe with the PEX 8311 bridging chip.

The PEX 8311's direct-memory access (DMA) capability offloads the host CPU's computational tasks that are required to transfer data between the PCIe port and the CPU-independent local bus standard used in many processor, DSP and FPGA designs.

The PCIe interface conforms to the PCI Express Specification r1.0a.

The PEX 8311 also features read ahead mode, programmable read pre-fetch counters, and deep FIFO buffers, which allow a zero wait state burst rate up to 264MBps.

The PEX 8311 comes in a 337-pin, plastic BGA package. Initial samples are available now with production slated for March 2006. Available in a Pb-free package, the bridge is priced at less than $25 in volume quantities.

- Ismini Scouras
eeProductCenter




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