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Where are the tools for next node?

Posted: 16 Dec 2005 ?? ?Print Version ?Bookmark and Share

Keywords:richard goering? ee times? philippe magarshack? st micro? stmicroelectronics?

If you're an EDA tool provider, it would be hard to find a more demanding customer than Philippe Magarshack, VP for central R&D at European semiconductor giant STMicroelectronics. ST is designing some of the world's most complex chips and is aggressively pursuing advanced process geometries, with 65nm designs in progress today and a 45nm test chip planned by year's end. EE Times caught up with Magarshack at the recent multiprocessor SoC (MPSoC) conference in Margaux, France, where the ST executive had plenty to say about EDA tool requirements, gaps in the design flow, the daunting challenges of 45nm, the future of SoCs and the importance of the Crolles2 process development alliance among ST, Freescale Semiconductor and Philips Semiconductors.

EE Times: What do you do at ST?
Philippe Magarshack: I'm in charge of the central group of ST's R&D organization. I deal with CAD solutions, library development and design flows. My customers are the internal design teams of the product divisions at ST. I provide them with transistor-level libraries as well as RTL-to-layout design flows. I also cover process technologies that we developed through Crolles2, including CMOS and BiCMOS.

How well are commercial EDA vendors meeting your needs?
Unless there is competition, they tend to arrive late. For instance, if it had not been for Magma Design Automation coming out a few years ago, I don't think the big guys, Synopsys and Cadence Design Systems, would have caught upwhich they did, and now we have a choice.
Today, we are working with Sierra Design Automation and they seem to be ahead of the pack in terms of multimode, multiple-corner optimization. We are starting to use one of their solutions, which is producing good results. In this case, we see that the big guysMagma, Synopsys and Cadenceare struggling to catch up.

What is missing from commercial EDA offerings today?
One would be an understanding and realization of process variabilitywhat we would call DFM [design-for-manufacturing]. There are some features now, such as double vias, DRC [design rule checking] or OPC [optical proximity correction] tools, but we don't see a flow that would take care of design intent from the beginning to the lithography at the end.
On the system-level side, I believe ST is one of the leaders in adopting SystemC for transaction-level modeling [TLM], but we lack tool support. We mostly use the open-source OSCI [Open SystemC International] simulator. We are looking at companies like Novas or Atrenta that are working on tools for design at this level, but we don't have a big toolbox yet.

What's the breakdown between external and internal EDA tools?
The historical trend is toward less and less internal, and more and more external tools. Years ago, we were developing our own simulators and synthesis tools. Now, we concentrate internal efforts on two areas. One is links with process, which is what we call DFM. The other area is detailed timing analysis and modeling, including statistical timing.
We also developed a whole environment for SystemC TLM internally. We are now transitioning to the newly adopted OSCI TLM standard. In addition, we are developing a complete solution internally for mapping C-language application software into homogeneous or heterogeneous multiprocessor SoCs.

What are you doing with statistical timing analysis?
We have an internal effort. And we are working with Synopsys and smaller companies. One of them is Extreme DA. It looks as if Extreme DA is closer to having a commercial tool and we are finishing correlation between what they do and Monte Carlo analysis.

If it works, will you abandon your internal development?
Absolutely. In that case, we can focus our R&D on other priorities. One of them could be EMC. That's an important specification in more and more systems.

Is there an overall message you'd like to pass along to EDA vendors?
The big vendors are not able to provide solutions that are needed at all times, thus, we use startups. The difficulty is that we lose a lot of effort in stitching together all the pieces among the startups we're using and mainstream vendors. One of our wishes is to have more standards to help with interoperability. In that respect, OpenAccess [an open, standard database] is providing some hope. We are adopting OpenAccess for our 65nm platform as the repository for the layout database.

What feature sizes are you currently working with?
We are doing production at 90nm. We are doing 65nm product designs as we speak. And we intend to do our first test chip for 45nm by the end of the year. The transition from 90nm to 65nm was relatively smooth compared with other chip makers' experiences. The dielectrics and metal rules are very similarjust a bit more complex. However, to get to 45nm, there are some major roadblocks. The only way to go around those roadblocks is with major disruptions in design flows.

What is so disruptive about 45nm?
The metal rules are becoming very complex to implement. Process engineers would like for all transistors with minimum-spacing rules to be aligned in the same direction. This is due to lithography equipment optical properties that are non-uniform in the X and Y dimensions.

And how would this transistor alignment affect the design flow?
Well, if we have to deal with that at 45nm, it will bring about a lot of difficulties in the way we floorplan the design. All the libraries would have to be laid out to have transistors in the same direction. Memory designs would probably be bigger than they should. Of course, we put I/O cells on four sides of the chip and we would also need to change the way we develop I/O cells.

Are there other concerns at 45nm?
There are other concerns and one of them is that the leakage of the transistor could reach the level of the dynamic power of the chip. We are definitely trying to think of ways to minimize this leakage by design. That includes multithreshold CMOS and multiple VDDs on chip.

Are commercial vendors providing 65nm and 45nm support today?
For 65nm, I would say that what needs to become mainstream is multimode and multicorner analysis. Some level of statistical analysis is probably needed. At 45nm, we don't see adequate support. We are negotiating with process engineers to make design rules easier to use.

What's coming up in terms of SoC architectures in the next year or two?
We will see a trend where IP [intellectual-property] blocks are moving to be at least partially programmable. What we're moving toward is having perhaps seven to 10 programmable processors on the same chip. The next thing is to have some programmable interconnect between these IP blocks, such as network-on-chip. ST is definitely looking into that and we support researchers working on that topic.

What kind of complexity are you seeing in gate or transistor count?
The most complex products are for networking customers, with die sizes above 200mm2 and transistor counts in the 350 million range. Medium-size products in the consumer market are about 50mm to 70mm2 with up to 100 million transistors. Small products, including analog circuitry for telecom applications, may be as small as 10mm2 and have about 5 to 10 million transistors.

With these big chips, what do you see in terms of time-to-tape-out?
For consumer designs, we are talking about something like a year and a half between the decision to make a chip and the time to tape-out. What we are doing is selecting fewer designs. Of course, each is bigger at the new process technologies and we're putting more designers on them. We are somehow able to have more IP reuse for these designs.

What is the Crolles2 effort and why is that important?
Basically, the R&D effort to develop a 90nm or 65nm node is such that a single company will not be able to fund that effort. Because we are able to share this effort with the best engineers from Philips and Freescale, the three companies have the latest in process development. At the same time, since we have engineers who are knowledgeable in this field, we also retain the capability to differentiate and add some process steps that allow us a competitive advantage.
We started with transistor-level design kits and technology files, and the next step has been to co-develop a portfolio of cell libraries. Because the process is identical, we can exchange those libraries. Next, we are finalizing an agreement to exchange commodity IP to put on a SoC. Today we have chips at 90nm in volume from the three companies. For 65nm, full production will be in Q2 of 2006.

- Richard Goering
EE Times

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