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Inphi tapes out high-speed chip with Cadence platform

Posted: 20 Dec 2005 ?? ?Print Version ?Bookmark and Share

Keywords:Cadence Design Systems? Inphi? Encounter digital IC? design platform? Encounter RTL Compiler?

Cadence Design Systems Inc. announced that Inphi Corp. has successfully taped out a complex high-speed chip using the Cadence Encounter digital IC design platform, including Encounter RTL Compiler global synthesis and the SoC Encounter hierarchical RTL-to-GDSII system.

Inphi's design, for the ExacTik INAMB581 server memory chip, achieved its goal of 666MHz with a TSMC 130nm process. Physical implementation of this mixed-signal design had the added complexity of a 529-pin flip-chip package.

"Implementation of our chip was extremely challenging given the aggressive frequency target and the complexity of a mixed-signal design with a flip-chip package," said Gopal Raghavan, founder and CTO of Inphi. "Encounter RTL Compiler global synthesis enabled us to meet our aggressive frequency target, while Encounter's automatic RDL routing for flip chips helped us meet our schedule. Altogether, the Encounter platform provided us with a powerful solution to help us meet our demanding goals."

Cadence's Encounter Digital IC design platform starts with Encounter RTL Compiler global synthesis, which delivers smaller, faster and cooler chips in less time. It is followed by the SoC Encounter hierarchical RTL-to-GDSII system, which delivers the fastest path to tapeout for large, complex ICs.

"We are excited that Encounter's global synthesis and physical implementation helped our customer achieve their aggressive frequency goal," commented Dr. Chi-Ping Hsu, corporate vice president at Cadence. "We are rapidly advancing our technologies to help customers win in their competitive markets."

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