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Council chooses model to succeed BSIM

Posted: 22 Dec 2005 ?? ?Print Version ?Bookmark and Share

Keywords:Compact Model Council? CMC? PSP model? Pennsylvania State University? Royal Philips Electronics?

The Compact Model Council (CMC) has selected the PSP model, jointly developed by Pennsylvania State University and Royal Philips Electronics, as the next generation industry standard CMOS transistor model, succeeding current industry standard BSIM3 and BSIM4 models.

In what was described as a hotly contested and close race, the PSP model edged the HiSIM-RF surface potential SPICE model, developed at Hiroshima University, by a vote of 17-14 among CMC members, according to Ken Brock, vice president of marketing at EDA supplier Silvaco. Both models had been elected by the council for standardization in May.

Brock, whose company advocated and sponsored the HiSIM-RF model, described the outcome as disappointing, but said Silvaco would support the PSP model.

"It basically came down to the ability of the models to perform at speed and capacity," Brock said. Brock added that the other major debating point was whether the model would be distributed in C, which he said is the way it has been done for 20 years, or distributed in Verilog-A and complied in C. By selecting the PSP model, the council chose the latter, which Brock described as "going into some uncharted waters."

Ivan Pesic, Silvaco CEO, said while he believes that HiSIM-RF is a slightly better model and easier for users to adopt, Silvaco has been preparing all along to support both models. In fact, he said, the selection of PSP may actually be strategically more beneficial to Silvaco, Pesic said, because the company believes it is further ahead of competitors on PSP (at least a year) and plans to release a "perfect" PSP model next month.

Pesic said the real question is which translator would be used to enable vendors to convert the PSP model from Verilog-A to C, something he said has not yet been established. Though vendors could work with the model without translating to C, he said, doing so would be "impractically slow."

The PSP (Penn State Philips) model becomes the industry standard for simulating the behavior of future generations of CMOS transistors produced at the 65nm node and beyond. According to Philips, the model will enable the optimal use of CMOS chip technology in real-world applications by allowing designers to accurately predict circuit performance before committing designs to silicon.

Philips said the new standard will also facilitate the exchange of chip designs between design groups and the outsourcing of chip fabrication to silicon foundries by allowing everyone to communicate using the same transistor modeling language.

"As CMOS takes on new roles beyond the production of purely digital chips, it is important that the industry has a single model that accurately predicts transistor performance under all circuit conditions, including RF and analog circuit behavior," said Reinout Woltjer, head of Philips Research's device modeling group, in a statement. "By basing the PSP model on the fundamental physics of transistor operation, it provides extremely accurate results over the entire operating spectrum from DC to well in excess of 50GHz."

BSIM3 and BSIM4 models have been standard for many years, but are considered unable to accurately model the behaviors of technologies at 90nm and below.

The CMC, founded in 1996 and comprised of 31 leading semiconductor companies and circuit simulator suppliers, is considered the world's foremost authority for the standardization, implementation and use of transistor models.

- Dylan McGrath
EE Times




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