Faraday tapes out ASIC production chips with Cadence platform

Cadence Design Systems Inc. announced that Faraday Technology Corp. has successfully taped out ten 130nm ASIC production chips with the Cadence Encounter digital IC design platform. Presently, ten other 130nm ASIC chips are currently being designed at Faraday using the Encounter platform.

The 130nmFaraday chips, with gate counts from 2 million to 5 million, are designed for a wide range of applications such as high-performance networking (450MHz), low-power mobile video and portable PC peripherals. The Cadence Encounter platform provided extensive timing/signal integrity (SI) closure and low-power features, which enabled Faraday to quickly implement low-power structured as well as standard cell ASICs, said the press release.

Victor Lin, VP of ASIC Technology at Faraday, added, "With Cadence's help we are able to achieve smaller die sizes, higher performance and lower power, which are exactly what customers expected."

The Encounter digital IC design platform provides a complete RTL-GDSII implementation solution. It includes Encounter RTL Compiler global synthesis technology for low-power-aware logic and physical synthesis, Encounter NanoRoute nanometer routing, and signoff-quality SI- and IR-aware timing with Encounter CeltIC and VoltageStorm analysis.