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SystemVerilog migration services from eInfochips

Posted: 13 Jan 2006 ?? ?Print Version ?Bookmark and Share

Keywords:eInfochips? Synopsys? SystemVerilog Catalyst Program?

eInfochips Inc. announced the availability of comprehensive verification migration services to speed the transition from other legacy languages and environments to IEEE Std 1800 SystemVerilog hardware design and verification language. eInfochips also disclosed that it has joined Synopsys' SystemVerilog Catalyst Program, and will extend its VeriSuite verification package to support SystemVerilog.

According to the press release, eInfochips' SystemVerilog migration services enable companies to easily take advantage of legacy verification environments while adopting the widely supported industry standard SystemVerilog hardware design and verification language. Services include translation of verification components such as bus functional models, bus monitors and random traffic generators, migration of existing test suites, and validation of migrated verification environments.

"eInfochips and Synopsys have worked together to move customers from legacy environments to a VCS Native Testbench (NTB) environment for up to five times faster verification performance through Synopsys' VCS NTB Migration Service program," said Steve Smith, senior director of Marketing, Verification Group at Synopsys. Smith added that by joining their SystemVerilog Catalyst Program, eInfochips will further enhance its SystemVerilog expertise and help ensure that customers experience its design and verification productivity and quality benefits.

eInfochips president and CEO Pratul Shroff, commented, "The constantly increasing complexity of SoCs has made verification more challenging. With SystemVerilog steadily gaining ground as the next-generation language for verification, we're confident of providing faster and more integrated verification to our customers migrating to the SystemVerilog standard."




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