Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Controls/MCUs

NoC: A new venue for system innovation

Posted: 16 Jan 2006 ?? ?Print Version ?Bookmark and Share

Keywords:SoC? noc? IP block? RISC processor? DSP core?

The SoC concept has evolved through a number of design challenges over the years and so has the number of semiconductor IP blocks, such as RISC processors, DSP cores, A/V codecs, USB interfaces and memories. The interconnection between these design blocks is commonly implemented by shared-medium buses.

But as we enter the ultradeep-submicron processes on 65nm and 45nm nodes, SoC devices with billions of transistors would require tens or hundreds of IP blocks.

Here, existing on-chip interconnect architectures, which use shared-medium buses for transmission among multiple IP blocks, are not without limitations. For SoCs with hundreds of IP blocks, bus-based interconnect architectures could lead to serious bottlenecks, as all devices share the same transmission medium.

Another critical issue with SoCs is non-scalable global wire delay. Global wires that carry signals across a chip do not scale with process nodes and are thus subject to a significant rise in delays. In ultradeep-submicron processes, about 80 percent of the delay of critical paths will be due to interconnects.

In a network-on-chip (NoC) setting, a group of IPs is connected to a neighboring switch so that communication between IPs can take place in the form of packets. The NoC concept is commonly defined as a flexible, scalable, packet-based network that replaces the fixed bus with a packet-based approach.

If startup activities are any indicator for the potential of a new technology, NoC has things going for it. Paris-based Arteris SA, for instance, was able to sell the NoC concept in the midst of the tech collapse in 2002. Design tools are available in the market from companies like Arteris.

Then we have STMicroelectronics building its existing on-chip communications expertise on a new platform it calls ST Network on Chip (STNoC) technologyalso dubbed as "Spidergon"to explore new SoC designs for convergence devices.

At a time when system-in-package (SiP) technology is considered a viable alternative amid SoC-related scaling worries, the whole idea of NoC could provide system chips with a new venue for innovation.

Some industry observers, however, caution against the hype and the subsequent difficulty in finding the right applications. Another area of concern is memory, as the data that moves around in this setting also needs to be stored somewhere.

Nevertheless, the NoC approach is emerging as a more flexible interconnect option for on-chip communications. The fact that convergence is at its best so far and SoCs have driven convergence also makes it a somewhat right time for NoCs.

That'd make it an important technology to watch this year.

- Majeed Ahmad
Electronic Engineering TimesAsia

Article Comments - NoC: A new venue for system innovati...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top