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Brute scaling not the answer, IEDM hears

Posted: 16 Jan 2006 ?? ?Print Version ?Bookmark and Share

Keywords:David Lammers? Nicolas Mokhoff? CMOS? power? Moore?

With CMOS power limitations in force, technologists are looking to a broader array of technologies to extend system performance in a new era that is being described as "More than Moore."

During the three days of the International Electron Devices Meeting (IEDM) in Washington, industry leaders urged the 1,700 IEDM participants to look beyond brute transistor scaling to new applications and user interfaces. In recent years, IEDM has broadened its own focus, staging as many as eight parallel sessions to accommodate traditional presentations on high-k dielectrics and the like, along with future-looking sessions on emerging technologies such as organic semiconductors and carbon nanowires.

In a stirring keynote address, Benedetto Vigna, a director at STMicroelectronics, said that "after the 'nomadic era' in which we are currently living, wireless sensor networks, domestic robots, smart pills and lab-on-chip applications are coming, aided by a new generation of low-power MEMS."

Electronics engineers must de-emphasize megahertz and realize there can be "serious energy costs" from brute Moore's Law scaling, said Stanford University professor Mark Horowitz. Instead, engineers must hone their ability to design parallel-processing systems that stay within the power limits of their applications.

Meanwhile, IBM Corp. technologists introduced a new performance-enhancing techniquecombining different silicon crystal orientations on bulk silicon wafers.

At IEDM three years ago, IBM researcher Min Yang described a somewhat more complex process of putting both 110-oriented silicon and the conventional 100 crystal lattice on silicon-on-insulator (SOI) wafers. IBM called that approach HOT or hybrid orientation technology, drawing upon the faster performance of PFETs in 110 silicon.

Last month, IBM took the HOT approach to bulk (non-SOI) silicon wafers, using a direct silicon bond technique. This DSB approach uses solid-phase epitaxy to convert 110 silicon to 100 silicon, said researcher Haizhou Yin. Yin called the approach "cost-effective," though it still requires bonding a handle wafer with a 100 substrate to a 110-oriented layer of silicon. A PFET placed on the 110 silicon showed a 35 percent current enhancement over conventional PFETs made on 100 bulk silicon, he said. Combined with the NFET on 100-oriented silicon, the net result was a 20 percent faster ring oscillatornearly equivalent to one generation of device scaling, said Yin. The solid-phase epitaxy conversion resulted in nearly defect-free 100 silicon, he said.

The approach is being looked upon favorably by Intel Corp., which has avoided SOI technology. Kaizad Mistry, manager of Intel's 45nm node, said that he believes IBM's DSB scheme has merit. "Mobility enhancement through strain will continue for a while," Mistry said. "We believe the industry can extend that over three generations. Then, the alternate crystal orientations and perhaps new planar structures will come in."

High-k doubts for 45nm
The biggest mystery hanging over the industry is whether high-k will be ready at the 45nm node, now in the final stages of development at Intel and elsewhere.

Nick Kepler, VP of logic technology development at Advanced Micro Devices Inc., said AMD makes six to eight changes in its process recipe over the lifetime of a process generation. While high-k is unlikely to be used in the first 45nm process, it could be ready at some later point, added in much the same way AMD retrofitted its 90nm process to accept the embedded silicon germanium stressors at the PMOS.

Bob Doering, a technology strategist at Texas Instruments Inc. and a U.S. representative to the International Technology Roadmap for Semiconductors (ITRS), said the industry is "in a big crunch. We've skipped a couple of generations without really scaling the gate oxide, and we will definitely be needing it in the 2008 time frame."

One possibility is that some chip manufacturers may introduce a fully silicided (FUSI) form of a metal gate electrode at the 45nm node, using a non-high-k gate oxide. Bringing in FUSI gates alone would reduce poly depletion effects.

"There is a fighting chance that what the industry calls the 45nm node will have a metal gate in the form of FUSI. It is coming along nicely," Doering said.

However, doped FUSI gates thus far do not provide the good work functionseparating the carriers to the edge of valence and conduction bandsneeded for high-performance silicon.

Mistry said Intel's work on FUSI metal gates with a silicon dioxide, presented at IEDM, showed that the work function for the PMOS transistor "is not good enough. We would have to improve on FUSI to make it a competitive approach."

IBM, for its part, does not have FUSI on its road map, according to Gary Bronner, an IBM project leader at the IBM-AMD alliance based in New York.

"IBM has done a lot of work on FUSI, but it is not on our list of options," he said in an interview.

Partners unite
Elsewhere at IEDM, Hisatsune Watanabe, president of the semiconductor research consortium Selected Leading Edge Technologies Inc., announced that Selete will continue beyond April 2006, thanks to additional backing from the Japanese government and the continued support of Fujitsu, NEC, Renesas and Toshiba, the four largest Japanese integrated device manufacturers.

Selete is one of many cooperative efforts under way in chip manufacturing. The East Fishkill alliance among IBM, AMD, Sony and Toshiba, the Crolles alliance in France and Toshiba's decision to share its process technology development effort with NEC in Yokohama are other examples.

"Competitors are engaging in 'coopetition' because R&D costs are growing at a rate that is simply unsustainable," said IBM VP Bernie Meyerson, speaking at an IEDM panel.

Gargini agreed. "We know what we have to do," he said. "It's a matter of executing to keep us on the projected road map for faster, cheaper and smaller chips."

- David Lammers and Nicolas Mokhoff
EE Times




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