Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Networks
?
?
Networks??

Micro Memory introduces VME carriers for FPGA processing

Posted: 17 Jan 2006 ?? ?Print Version ?Bookmark and Share

Keywords:MM15x0? MM-16x0? CoSine-on-Othello? VME carrier board? field programmable gate array?

Micro Memory introduced its CoSine-on-Othello MM15x0 and MM-16x0 VME carriers for FPGA processing on serial switch fabrics. Both the MM-15x0 and MM-16x0 support continuous data streams through independent, non-blocking pathways. Targeting applications such as synthetic aperture and phased array radar, software-defined radio, signal intelligence, and semiconductor and medical imaging, these devices utilize FPGAs for DSP operations such as FFTs, filters, and image or data compression.

The products are said to be the first VME boards to include the V-4 SX series of FPGAs from Xilinx. Additionally, they are the first to include the V-4 LX series of FPGAs, which stand apart in their logic resources for applications requiring the maximum possible gate count.

The MM-15x0 and MM-16x0 carriers both feature two high-speed mezzanine sites, each of which can be configured for a PMC or XMC. Configured for PMC support, each PCI bus can operate in PCI 2.3 mode at up to 66MHz or in PCI-X mode at up to 133MHz, while configured for XMCs, the sites can support the Aurora protocol or Serial RapidIO x4. Each site has a dedicated pathway directly to FPGA processing resources that is unobstructed by any bus translation bridges, significantly improving latency and throughput.

The products include two independent CoSine compute nodes (CCNs). Each CCN is comprised of a CoSine primary device (V-II Pro 2VP70) that includes two interface ports (PCI-X, Serial RapidIO, or Aurora), two embedded PowerPC processors, a CoSine companion device (V-4 SX55 or V-4 LX160), seven independent memory arrays, and two processor programmable flash arrays.

One multi-ported primary DDR array for seamless bus translation between the mezzanine port and backplane port, a dedicated DDR array for each PowerPC processor, and four independent QDR II SRAM arrays local to the SX55 or LX160 for FPGA processing operations make up the seven independent memory arrays in the CCN. Aggregate memory bandwidth exceeds 20Gbps per CCN, providing a total of over 40Gbps on the MM-15x0 and MM-16x0.

Each of the embedded PowerPCs in the 2VP70 device is a fully functional computer with its own DDR array, programmable flash, UART, and shared Ethernet. Processors can host device drivers, perform message passing, service interrupts, or execute floating point operations. Each processor includes a complete BSP with fully integrated internal SoC device drivers.

In addition to a VME320 2eSST interface, the MM-15x0 and MM-16x0 are touted to be the first VME boards to include complete on-board serial RapidIO switch fabric connectivity. The VxS VITA 41 MM-1500 and MM-1550 include two independent serial RapidIO ports on P0 per the VITA VxS 41.2 specification. Alternatively, two Aurora ports can be configured to P0 per the VITA 41.5 and VITA 55 draft standards. The MM-1600 and MM-1650 each include four independent serial RapidIO ports on to the backplane per the VITA VPX 46.3 specification.

The SX55s and LX160s also have additional FPGA platform flash to store multiple bitstreams. Because the principal SoC functionality is largely contained in the 2VP70 CoSine primary device, the MM-15x0 and MM-16x0 are designed for reconfigurable processing. This approach enables the SX55 or LX160 CoSine companion devices, which contain user programmable logic, to be reconfigured by the 2VP70 CoSine primary devices without the 2VP70s needing to be reconfigured.

The extended temperature air cooled DR models have operating temperatures of -400C to 710C, and the conduction cooled DT models have operating temperatures of -400C to 850C.

Initial list pricing for Micro Memory's CoSine-on-Othello MM15x0 and MM-16x0 VME carriers is $34,500 per unit with volume discounts available.




Article Comments - Micro Memory introduces VME carriers...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top