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Asynchronous EDA tools coming in Q2, says Silistix

Posted: 18 Jan 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Peter Clarke?

EDA and IP startup Silistix Ltd, a spin-out company from an asynchronous logic research group at the University of Manchester in England, has announced further details of its asynchronous interconnect design tools.

The company first announced the Chain Works tools in December 2005. The company has now said the tools, which allow different pieces of clocked logic to be joined together asynchronously, would be available in the second quarter of 2006 and priced similarly to Design Compiler from Synopsys Inc. Chain stands for Chip Area Interconnect.

Silistix did not state whether it had achieved any tape-outs on its own behalf or working with lead customers. Silistix was founded in December 2003 and has received backing from Intel Capital.

The Chainworks design environment comprises two tools that are used in a conventional ASIC/SOC design flow together with a library. A chip designer uses Chain Designer to take a description of the connectivity and ports of a design and generates the structure of the Chain asynchronous interconnect fabric along with link widths and fine-grained pipeline stages to balance area, speed and power tradeoffs. Using a graphical user interface, the designer can place network gateways, connect ports to client entities, and either manually or automatically create a Chain topology. Chain Designer generates a Verilog or SystemC descriptions of the fabric for simulation, simulation testbenches, and constrained Chain netlists for input to Chain Compiler.

The China Compiler takes the constrained Chain netlist generated by Chain Designer and components from the Chain Library to produce the structural netlist suitable for inclusion into the targeted SoC. The structural netlist is then input into to a conventional logic synthesis tool such as Synopsys' Design Compiler and mapped to standard cells. Chain Compiler also creates scripts for static-timing analysis and hints for downstream place and route operations, Silistix said.

"With Chain Works SoC designers can implement self-timed Chain interconnect fabrics that provide significant power and design advantages over chips that are data-rate limited by a global system clock," said David Fritz, vice president of marketing at Silistix, in a statement. "To accelerate the adoption of our technology we have developed design tools that let designers combine our self-timed Chain fabric with conventional synchronous IP cores on the same chip.

- Peter Clarke
EE Times

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