Statistics engine liberates processor in IP-based networks

Integrated Device Technology Inc. (IDT) has developed a chip that tracks statistics in IP-based networks, allowing packet processors to focus on other computer-intensive tasks.

Tailored for edge router, broadband access equipment and multi-service provisioning platforms, the statistics engine is IDT's way of giving more intelligence to the network to deliver services to three types of users: consumer, business and mobile. They all require services that go beyond just filing downloads, such as billing, security and QoS levels, said Jeremy Bicknell, product manager for flow control management group at IDT.

"The challenge we're talking about today is really the extra intelligence that enables these services," Bicknell said. "One of the key requirements is to track statistics accurately."

The traffic is different in simple file downloads compared with IP-based networks that are processor-intensive to perform advanced services such as web-based business and e-commerce, telecommuting, IP-based voice, video and data and storage.

"With VoIP service or delivering video service, the packets tend to be more minimum length packets. So instead of the thousands of bytes that a segmented file downloads, we have 64-byte packets for VoIP and signaling. So what we need to do with all of these packets is to be able to count them," Bicknell said.

On the line card, there's an aggregate of data that provides services to many users. Designers would typically use an NPU and QDR-II SRAM, an FPGA and QDR-II SRAM, or ASICs with proprietary statistics interfaces to address these statistics functions. According to Bicknell, conventional methods impede packet processor performance.

IDT's task was to develop a device that associates counters with the many thousands of flows that deliver the services to the end user. Based on its network search engine devices, which are used for classifying packets, IDT developed the statistics engine that is the first in a family of data-path accelerators.

There are two devices: the 70P1308 has up to 512,000 counters and the 70P1338 has up to 256,000 counters. The devices are designed to replace traditional memory-based statistics methods. The statistics engine frees up the processor to focus on other functions, such as policing, address translation and look-up of short packets at wire speed, like fiber, Bicknell said.

"If you're looking at multi-gigabit line card, there's a challenge in processing packets in which 50 percent of that data is composed of minimum length packets. There's not much time to process those packets and count them," said Bicknell. With conventional statistics methods, the processor is busy updating the counters to memory.

IDT's statistics engine eliminates the processor's tasks by using a dual-port memory-cell architecture to provide a "fire and forget" capability. Bicknell said that the company sees a 90 percent improvement in the processor cycle and more than 80 percent efficiency in bus utilization. He attributes the improvements to a 64-bit arithmetic logic unit (ALU) inside the device that not only allows a 64bit counter to be updated in a single cycle, but can update up to four counters in a single clock cycle.

"That improves the efficiency of the bus that we use to connect to the processor, and it ensures coherency, which means that we can update these counters and read them at any time and you're assured that they are the correct value," Bicknell added.

The statistics engine is available in a 576-ball, RoHS-compliant flip-chip package. The device is sampling now, with production available scheduled for the second quarter of this year. It will be priced at $55 to $65 in 25,000-unit quantities.

- Ismini Scouras
eeProductCenter