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XFP transceiver IC features jitter attenuating capability

Posted: 20 Jan 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Silicon Laboratories? SiPHY? physical layer? Si5040? DSPLL?

Silicon Laboratories Inc. announced what it touts as the industry's first 10Gbps XFP transceiver IC with integrated jitter attenuating capability on both transmit and receive data paths.

With a package size of 5-by-5mm, the Si5040 is one of the industry's smallest solution offering low power and low jitter for space-constrained XFP applications. Additionally, the Si5040 transceiver supports continuous operation with jitter attenuation across all telecom and datacom protocols between 9.9Gbps and 11.4Gbps, including OC-192/STM-64, 10GbE, 10G Fiber Channel and their corresponding forward error correction data rates.

Achieving best-in-class jitter performance, the Si5040 uses the company's patented DSPLL technology to reduce jitter on 10Gbps serial data streams that have been degraded by system level noise sources on either the network side or the port card. This revolutionary new transceiver architecture provides industry-leading transmit jitter generation of 2.5mUI RMS while eliminating the need for external jitter clean up circuitry inside the module or on the port card. Applying DSPLL technology in the receive path minimizes receive data jitter to ensure error-free operation with port card ASICs or FPGAs.

"The Si5040 continues to deliver on Silicon Laboratories' commitment to providing innovative solutions to the networking industry by leveraging our industry leading DSPLL technology," said Dave Bresemann, VP of Silicon Laboratories. "By combining jitter attenuation capability together with a sophisticated receiver architecture, we are greatly simplifying the task of achieving true SONET/SDH performance in XFP module applications."

The Si5040 XFP transceiver supports three types of analog and digital signal quality monitors, including analog loss-of-signal detection, consecutive identical digit detection and a proprietary digital measure of receive data eye opening. This device also simplifies system level test and debug by offering line loop-back, XFI loop-back and PRBS pattern generation and checking on both transmit and receive data paths. Complete device configuration and status monitoring is available through a serial microcontroller interface supporting commonly used protocols such as I2C.

The Si5040 consumes less than 575mW typical. It promises to further simplify power management by operating over a wide power supply variation from 5 percent to -10 percent, and provides additional power savings through programmable signal swings on all high-speed outputs. By operating over the full industrial temperature range (-40C to 85C), the Si5040 accommodates demanding module thermal conditions.

The Si5040 is available in a 5-by-5mm, Pb-free, RoHS-compliant, 32-pin QFN package. Samples are already available, with production scheduled for Q2 2006. Pricing for the Si5040 is $38.25 in quantities of 1,000.




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