Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > T&M

Firmware endows PCI bus digitizers with TDC conversion

Posted: 30 Jan 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Alex Mendelsohn? Acqiris? TDC? time-to-digital conversion? Model AP240?

Data conversion supplier Acqiris now offers peak analysis and TDC (time-to-digital conversion) firmware for its existing Model AP240 and Model AP235 dual-channel reconfigurable PCI bus analyzer plug-ins. The new bits are priced at $2,990.

The AP240 and AP235 platforms themselves provide up to 1GHz of bandwidth and dual-channel capability, with synchronous acquisition up to a 1GS/s sampling rate (up to 2GS/s in a single-channel mode). They use the company's proprietary XLFidelity and JetSpeed A/D (analog-to-digital) converter chipsets. These boards also include front-end signal conditioning with calibrated gain and offset ranges.

FPGA processing units
Each channel has an independent digitizer and separate programmable processing based on FPGAs. The FPGAs enable the analyzers to be re-configured to perform a variety of on-board realtime signal processing.

The AP240 board is the highest performance plug-in, with its 1GHz front-end bandwidth and 1GS/s analog-to-digital converter. It packs up to 12MB of memory, with up to 48MB as an option.

For its part, the AP235 uses a similar architecture as the AP240, but is a more economical package intended for lower-frequency applications. The AP235 unit's front-end bandwidth is 500MHz and its maximum sampling rate is 500MS/s.

For single-channel applications, both cards can interleave their two A/D channels, doubling the maximum sampling rate (2-Gsamples/s for the AP240 and to 1GS/s for the AP235) on either input under software selection. This also doubles timing resolution.

These cards are PCI-compliant and can be installed directly in a full-length PCI slot on a PC running under Windows, Linux or Wind River VxWorks. The PCI bus permits processed data to be transferred to your host PC at sustained rates of up to 100MBps.

The cards can also be controlled over the PCI bus or directly from the front panel using Acqiris's Ctrl I/O system. Ctrl I/O provides two analog connectors for clock/reference and trigger signals, as well as four digital lines for monitoring card status or configuration.

Enter the firmware
Acqiris's PeakTDC firmware makes the analyzers suitable for use in systems where signal bursts are acquired and analyzed, and where data reduction to peak information is needed. This includes time-of-flight and imaging applications such as TOFMS (time-of-flight mass spectrometry), ultrasound, LIDAR (light detection and ranging) and sonar.

The AP240 PCI analyzer's re-configurable on-the-fly processing, based on an FPGA DPU (data processing unit), is where the firmware operates. Running the PeakTDC firmware, the DPU can now isolate peaks from waveform data obtained at up to 2GS/s (1GS/s for the AP235), and transfer this peak data in the form of time and/or amplitude to your host PC.

To obtain maximum data throughput, the digitized waveform data is processed using a so-called ping-pong buffer system. The firmware also supports various post-acquisition processing and data storage techniques, affecting how data is treated and transferred to the host PC.

The Hysteresis algorithm
Peaks are located using a hysteresis algorithm that measures true peak position and amplitude, and permits multiple peaks to be defined within a wide range. This is useful when averaging or creating a histogram from a series of similar waveforms.

In operation, the PeakTDC firmware initially finds peaks with gate regions defined during the acquisition. After data are acquired, the DPU begins looking for peaks. After the signal has increased from its minimum by some programmable value, the algorithm searches for the peak value in the digitized data stream.

After the signal level drops below the current maximum, the maximum value in the block of data is validated as a peak. The algorithm then continues looking for another rising start delta. Using this method, multiple peaks can be defined within a large zone of interest, even when densely packed in the waveform data.

For location of the true peak maximum, peak time and amplitude are determined using an interpolation routine. Fitting a 12bit quadratic spline to the points around the extrema found by the hysteresis algorithm, the position of the peak maxima is found and defined by its time and amplitude.

Acqiris says this provides improved time resolution, and is especially useful when averaging or creating a histogram from a series of very similar waveforms.

- Alex Mendelsohn

Article Comments - Firmware endows PCI bus digitizers w...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top