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Vendor sees ESL design taking hold

Posted: 01 Feb 2006 ?? ?Print Version ?Bookmark and Share

Keywords:dylan mcgrath? ee times? esl? japan? esl design?

Adoption of ESL design methodology in North America has accelerated within the past few months, according to Michael Sanie, VP of marketing and business development at Calypto Design Systems Inc. Sanie said his assessment is based on interest in his company's sequential logic equivalence checking (SLEC) product.

Sanie said North America still lags Japan and Europe in ESL adoption, but that the technology is starting to gain traction in the United States. Japan remains strongest in ESL, he said, because designers in that country had a head startthey showed interest in ESL the earliest primarily because moving to a higher level of abstraction is seen as a way to help cope with the extremely short (as little as three to four months) design cycles many chips are now facing. By contrast, he said, designers working on microprocessors, which have 18-24 month design cycles, still prefer to work at a lower level of abstraction to maintain more detailed control.

"It was only a matter of time," Sanie said. "The need is there, and the technology is coming together. Most of design today is still being done in RTL, but a lot more is beginning at a higher level."

Stressing that ESL adoption, even in Japan, is still in its infancy, Sanie said ESL is not being used in mainstream design, but early adopters are taking a close look at it and, in some cases, using it in production.

Sanie credited the availability of more ESL tools and methodologies for the technology's momentum in North America. "It's one thing to have the tools, but you also need to have the methodology," Sanie said. "Inevitably, the need to move up to a higher level of abstraction is going to be there."

Since its introduction in April, Calypto's SLEC has garnered attention from industry observers because it purports to offer a fundamentally different approach to equivalence checking. The tool serves two purposes: to verify that an RTL block is functionally equivalent to a higher-level block written in VHDL, Verilog, SystemC or C/C++, and to verify that sequentially different versions of an RTL block are functionally equivalent. In other words, SLEC is said to not only check the functional equivalency of blocks written in different languages, but also ensure that a modified RTL block remains functionally equivalent to the original.

According to Sanie, the product has also attracted plenty of interest from the customer basehe said Calypto has had SLEC engagements with 15 of the top 20 semiconductor manufacturers. Several of these engagements have resulted in sales, Sanie said, although Calypto is unable to disclose most of them. Calypto has publicly announced two major SLEC customersRenesas Technology Corp. and Freescale Semiconductor Inc., which said in June it was using SLEC in its PowerPC e700 processor platform.

"Most of our engagements have been with the larger companies," Sanie said, adding that Calypto's strategy is to get adopted and "go deep" with the major players. Sanie said SLEC has had engagements with North American, Japanese and European chipmakers, and that the tool has already been used in production with some customers.

The knock against SLEC has been capacity. Calypto told EE Times that the "sweet spot" for the tool is blocks with 50,000 to 200,000 gates, and Calypto CEO Devadas Varma acknowledged that SLEC could "run out of steam" on a design that exceeds several hundred thousand gates or contains large sequential differences from the design it is being check against.

- Dylan McGrath
EE Times

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