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Xilinx announces new DDR2 reference design

Posted: 06 Feb 2006 ?? ?Print Version ?Bookmark and Share

Keywords:DDR2-SDRAM interface? ChipSync? Xilinx? reference design? Virtex-4?

Xilinx Inc. announced the availability of its Virtex-4 FPGA-based 667Mbps DDR2 reference design. The 667Mbps DDR2-SDRAM interface uses the Virtex-4 ChipSync technology, a run-time calibration circuit that promises to improve design margins and overall system reliability.

According to the press release, the combination of Virtex-4 silicon features, reference designs and the Xilinx Memory Interface Generator tool provides design flexibility and reliability. Xilinx memory solutions are verified in hardware using memory devices from companies like Micron and Samsung, including the 667Mbps DDR2 reference design.

Xilinx said that the ChipSync technology simplifies the implementation of memory interfaces by compensating for routing, process, temperature and voltage variations that produce skew between data and clock signals that may not be correctly estimated at design time. This feature alleviates post-design adjustments, and improves design cycles and overall system reliability, explained the company.

The Memory Interface Generator software tool supports any device/package combination. The reference designs are available in Verilog or VHDL.

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