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Intel CTO calls for better chip-design tools to beat process variance

Posted: 08 Feb 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Rick Merritt? chip-design tool? Intel?

The industry needs to deliver a new generation of chip-design tools to ease power and variance problems, according to Intel's CTO.

Intel will do its part to drive down power problems when it announces its next-generation microarchitecture at the Intel Developer Forum in early March, added Justin Rattner, in an interview after a keynote address at DesignCon.

Intel saw productivity for its chip designers jump 30 percent in one recent CPU, only to see nearly all that advantage eaten away by the need to realign transistors to accommodate process variances to get a 10ps timing closure, Rattner said. The company has seen frequency variations of as much as 30 percent because "fewer and fewer atoms are responsible for the actual semiconductor effects," he added.

"We need to develop tools to relieve designers from concerns about these variabilities," Rattner said.

In an interview, Rattner said the new design-for-manufacturing tools should "apply very powerful statistical guide device sizing" and placement on a chip.

For its part, Intel is preparing a next-generation Pentium microarchitecture that aims to significantly reduce power consumption for the X86 chips notorious for running fast but hot. "We are really focused on minimizing energy per instruction. That's the new mantra," said Rattner.

"The jump from Dothan [Pentium M] to Yonah [Intel Duo Core processors] was nice, but not astounding. But the next jump is pretty astounding," and could reduce the power and thermal envelopes OEMs need to accommodate in their server and desktop chips, Rattner said.

Rattner also referred to two papers on power Intel is presenting at this week's International Solid State Circuits Conference (ISSCC) in San Francisco.

One paper discusses how Intel provided two separate power-supply rails on a recent CPU. A high-power rail served most of the chip, while a low-power rail supplied a cache, allowing for a 35 percent reduction in cache size.

The second ISSCC paper discusses a prototype method for supporting multiple power supply rails on chip by using a new all-CMOS, fast voltage regulator. The research device can switch power on or off in nanoseconds rather than milliseconds required for discrete voltage regulators.

The technique would be especially useful for running different cores at different supply voltages on multicore CPUs, Rattner said. "This is a very important technology for which we have high hopes," he added.

However the CMOS voltage regulators require a new magnetic thin-film layer as well as off-chip inductors. Bringing the new thin films into high volume fabs and getting the inductors on chip are major challenges toward commercializing the technology over the next three to four years, he added.

- Rick Merritt
EE Times

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