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Sirific used Cadence's simulator in designing its RF transceiver

Posted: 08 Feb 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Cadence Design Systems? Sirific Wireless? fables? CMOS? RF transceiver?

Cadence Design Systems Inc. announced that Sirific Wireless Ltd, a fabless RF semiconductor company, has successfully designed its single-chip CMOS RF transceiver for HSDPA/WEDGE using Cadence's Virtuoso UltraSim Full-chip Simulator for FastSPICE simulation.

According to the press release, the Virtuoso UltraSim simulator enabled Sirific to cut its verification time from two weeks to eight hours, allowing development in record time while ensuring silicon accuracy critical for mixed-signal designs.

Michael Hogan, president and CEO of Sirific, commented, "Virtuoso UltraSim greatly improved the efficiency of our designers by providing them the best combination of performance, convergence and accuracy, giving us confidence in our design leading to first pass silicon success"

The Virtuoso UltraSim simulator is an integral part of Cadence Virtuoso Multi-mode Simulation, offering all the simulation components necessary for validating an IC or system. Cadence added that Virtuoso Muti-mode Simulation provides a unique combination of SPICE, FastSPICE, AMS and RF simulation in a flexible single multi-mode simulation licensing model that maximizes the value of a customer's investment.

"Virtuoso UltraSim is our next-generation FastSPICE simulator that provides custom designers the ability to verify their complex mixed-signal SoCs with the silicon accuracy they need to quickly get their products to market," said Zhihong Liu, corporate VP of R&D for Virtuoso Multi-mode Simulation at Cadence.




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