Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Memory/Storage

TI, MIT, DARPA collaborate on 65nm SRAM

Posted: 13 Feb 2006 ?? ?Print Version ?Bookmark and Share

Keywords:SRAM? 65nm? SmartReflex? CMOS? MIT?

During the International Solid States Circuit Conference, researchers from the Massachusetts Institute of Technology (MIT) presented an ultra low power (ULP) 256Kb SRAM test device manufactured in Texas Instruments' (TI) 65nm CMOS process. Developed for battery-operated devices, the SRAM is said to feature the industry's lowest reported voltage, and is being considered for TI's SmartReflex power management technologies.

The resulting 0.4V sub-threshold SRAM achieves 2.25 times lower leakage power compared to its 6T counterpart at 0.6V. The SRAM incorporates 10 transistors per bitcell to enable operation down to 400mV.

"Ultra low power operation is critical in a variety of emerging commercial and military applications," said MIT professor Anantha Chandrakasan. "With funding from the U.S. Defense Advanced Research Projects Agency (DARPA) and TI, MIT graduate students have developed ultra-low-voltage logic and memory circuits in 65nm CMOS that function below 400mV. Scaling to such low supply voltages is critical to minimum energy processing and enables ultra-dynamic voltage scaling. The goal of this ULP technology is to reduce energy by an order of magnitude with minimal loss in system performance."

Based upon a multi-year collaboration between MIT and TI, and partially funded by DARPA, the SRAM development is part of a larger objective to create ULP logic and memory for battery-operated devices. The joint program is focused on reducing voltages to the sub-threshold level to save much-needed energy and enable simultaneous ULP and high performance, and includes development of memory modules and others such as logic and switch-mode power supplies.

The MIT work includes analysis of the optimal energy point of a given system, modeling energy characteristics of sub-threshold circuits and developing circuit styles and architectures. Research is focused on emerging applications, where energy efficiency concerns now supersede the traditional emphasis on speed.

The device is based on TI's 65nm process. The company used SmartReflex dynamic power management technologies that automatically scale power supply voltage based on users' performance demands and is said to help control power consumption.

According to Uming Ko, TI senior fellow and director of TI's wireless chip technology center, leveraging these techniques in future mobile SoC designs will extend TI's abilities to enable new wireless entertainment, communications and connectivity features.

In December TI qualified its 65nm process technology and moved to volume manufacturing. The 65nm process is said to deliver more processing performance for advanced applications in a smaller space without increasing power consumption.

TI first disclosed the process technology in early 2004, and announced sampling of the 65nm wireless digital baseband processor in March 2005. The process technology is said to double transistor density over the company's 90nm process, shrinking equivalent designs by half and boosting transistor performance by up to 40 percent.

Article Comments - TI, MIT, DARPA collaborate on 65nm S...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top