Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

New patterning synthesis solution for 65/45nm

Posted: 14 Feb 2006 ?? ?Print Version ?Bookmark and Share

Keywords:DimensionPPC? patterning synthesis? PPC? process and proximity compensation? Invarium?

Marking its debut as a provider of patterning synthesis solutions to the semiconductor industry, Invarium Inc. unveiled DimensionPPC, a unified, full-chip process and proximity compensation (PPC) product for patterning IC layouts at 65nm and below. This new product aims to overcome the deficiencies of RET/OPC tools and layout correction techniques for other process effects, from mask through etch.

The DimensionPPC's "correct-by-construction" approach reduces the cycle time from layout completion to volume production by simplifying the tape-out flow, reducing RET/OPC missteps, and averting mask and silicon re-spins.

DimensionPPC is patterning-process-centric technology comprised of a PPC model and a mask layout synthesis engine. The PPC model claims to accurately simulate how an IC layout will be patterned post-etch and across the process window. The mask layout is then optimally synthesized in a single, unified step that embodies RETs and inversions of actual process effects.

DimensionPPC runs on standard computer clusters and distributed processors, and does not require custom hardware. The product was fab-validated at 65nm during Q4 2005. The technology is currently in production deployment at one customer site and is being qualified for production use by five additional semiconductor manufacturers.

Invarium said that the DimensionPPC is designed for 65nm and 45nm advanced nodes, and is built on a technology foundation with a vision to 32nm and EUV lithography.

Article Comments - New patterning synthesis solution fo...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top