Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Cadence's Virtuoso RET Suite puts 'design back into DFM'

Posted: 17 Feb 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Cadence Design Systems? Virtuoso? Resolution Enhancement Technology? RET? lithography?

Cadence Design Systems Inc. introduced its Virtuoso Resolution Enhancement Technology (RET) Suite, which integrates lithography awareness directly into the Cadence Virtuoso custom design platform.

With the Virtuoso RET Suite, said the press release, designers targeting sub-90nm manufacturing technologies are now able to create layout designs that are less sensitive to critical yield-degrading lithography issues, and which are de-sensitized to common lithography-process variations.

The Virtuoso RET Suite allows designers to analyze and optimize designs for both performance and yield by examining precisely how target layout structures will appear in silicon. This is done by modeling the distortions that are inherent in today's sub-wavelength lithography. Cadence added that the suite includes interactive model-based simulation of layout designs, batch and interactive lithography rule checking, lithography-yield analysis and optimization, and trial-based optical-proximity-correction capabilities utilizing critical lithographic parameters, including illumination mode, exposure and focus.

The Virtuoso RET Suite is based on technology developed through the company's previously announced developmental agreement with ASML, a provider of lithography systems for the semiconductor industry. With its tight integration into the Virtuoso environment, the Virtuoso RET Suite offers the same, familiar and intuitive user interface and use model that most layout designers routinely use today, thereby promoting easy adoption. Marc Levitt, VP for design for manufacturing (DFM) at Cadence, said, "The Virtuoso RET Suite graphically illustrates our strategy of putting the 'Design' back into 'DFM.' Traditional post-processing DFM solutions have proven insufficient to address the demanding requirements of the most advanced semiconductor lithography and manufacturing. Creating high-yield, high-performance designs requires that layout designers be aware of manufacturing effects. The Virtuoso RET Suite directly addresses this need by allowing layout designers to see exactly what the resulting silicon will look like when manufacturing effects are considered."

Article Comments - Cadence's Virtuoso RET Suite puts 'd...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top