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Simplify partial reconfiguration for Xilinx's FPGAs

Posted: 17 Feb 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Xilinx? PlanAhead? design? analysis? ISE?

Xilinx Inc. announced immediate availability of the latest version of its PlanAhead software, a hierarchical design and analysis solution that along with Xilinx's Integrated Software Environment (ISE) software promises to deliver a two speed-grade performance advantage for Xilinx FPGA-based MPEG-4 encoder" target=_blank>Virtex-4 and Spartan-3 FPGAs over competing offerings.

The company added that the new release enables significant savings in cost, size and power consumption by simplifying partial reconfiguration for Xilinx FPGAs. Additional PlanAhead 8.1 productivity enhancements include the ExploreAhead feature, which allows designers to employ multiple design strategies to meet their timing goals in the shortest possible time.

"Many FPGA design teams tell us they are willing to integrate a new tool into their design flow if it helps them meet their timing targets with greater certainty in a shorter time," said Bruce Talley, VP of the design software division at Xilinx. "They want a tighter correlation between logic and physical domains, and help in automating design iterations. PlanAhead 8.1 builds on the capabilities of our ISE Fmax Technology and demonstrates that a little additional time spent interacting with one's design pays big benefits in performance, functionality and cost."

Achieve your target Fmax with fewer design iterations
According to the press release, PlanAhead streamlines the step between synthesis and place-and-route to give designers more control and insight into how designs are implemented to achieve their target Fmax with fewer design iterations. The tool allows designers to utilize a hierarchical design methodology to minimize routing congestion, simplify clocking and interconnect complexity, and explore implementation options.

Xilinx added that the PlanAhead 8.1 software introduces new features and capabilities that streamline the partial reconfiguration design flow. Partial reconfiguration allows customers to save on device count, size, power and cost by allowing predefined portions of an FPGA to be reconfigured while the remainder of the device continues to operate. The new release claims to simplify the creation of dynamic modules and allows customers to create multiple floorplans for each of their design implementations.

Specifically, PlanAhead 8.1 enhancements offer additional design rule checking, overlap detection, automatic macro creation for module-to-module IO, and a new place-and-route wizard. PlanAhead also controls and manages these implementations in ISE in a simple and easy to use design environment. According to Xilinx, these improvements make partial reconfiguration more accessible for a wider range of applications, including automotive control functions and software defined radio, where it is already being rapidly adopted.

In addition, the new ExploreAhead feature enables designers and design teams to manage and reuse multiple design strategies while maximizing their computing resources.

Other productivity enhancements include improvements to the schematic viewer for more efficient and intuitive navigation, design analysis and debug and a graphical representation of design hierarchy for enhanced design exploration.

The PlanAhead 8.1 design analysis tool is available on all major OSes as an option to Xilinx's ISE software. Single-user licenses at $5,995 include training. Customers can try PlanAhead by downloading a free 30-day evaluation at Xilinx's website.




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