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4Gb NAND flash memory achieves 36MBps throughput

Posted: 20 Feb 2006 ?? ?Print Version ?Bookmark and Share

Keywords:ST? Flash memory? STMicroelectronics?

STMicroelectronics (ST) unveiled details of an advanced 4Gb NAND Flash memory that achieves a 36MBps throughput, said to be 50 percent greater than the best results achieved to date. According to the press release, the device incorporates a powerful embedded error-correction processor that can detect and correct up to five errors per page to ensure high reliability and fast data throughput while simplifying the design of the memory system.

The new NAND Flash memory employs a different approach in which a sophisticated error correction code (ECC) processor is embedded within the Flash memory. In addition, said ST, the embedded ECC processor is based on an innovative architecture that optimizes the ECC computations for byte-oriented, serial readout memory applications such as MP3 players and USB keys, minimizing silicon area, latency and power consumption.

"This innovative breakthrough will fast become standard in ST's two bit per cell NAND Flash roadmap," said Carla Golla, GM of ST's NAND Flash memory division. "Moreover, we fully expect this type of approach to be implemented as an industry standard feature in 2bit per cell devices, which are rapidly increasing their share of the NAND Flash market. This method realizes the cost advantages of multilevel cell technology, but without sacrificing system read throughput and reliability."

Developed at the company's non-volatile memory facility in Agrate, Italy, the 4Gb NAND Flash memory achieves its record-breaking throughput with minimal overhead in terms of silicon area, power consumption and latency, said the press release. The area occupied by the ECC circuitry is 1.3mm2, and the average current drawn by the chip is <1mA. The error correction circuitry is also partitioned to minimize time penalties when errors are detected. Two separate error location blocks are provided, one of which corrects 2 to 5 errors with a 250?s time overhead and one which corrects the much more likely single error in 34?s.




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