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Immersion lithography 'nearly ready,' says TSMC

Posted: 24 Feb 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Mark LaPedus? Taiwan Semiconductor Mfg? TSMC? immersion lithography?

Most experts believe that immersion lithography is still a year or two away from actual chip production. Many chip makers are scrambling to get the technology in production at the 45nm node in 2007 or so.

But Taiwan Semiconductor Manufacturing Co. Ltd (TSMC) said that immersion lithography is "nearly production ready." TSMC claimed that its immersion lithography program has produced test wafers well within acceptable parameters for volume manufacturing. The findings support TSMC's proprietary techniques for nearly defect-free immersion lithography, which has been a concern for chip makers.

TSMC's immersion lithography technology is targeted for its 45-nm manufacturing process, which is slated for 2007 or so. The silicon foundry provider is expected to use 193-nm immersion tools from its sole vendorASML Holding NV. TSMC is reportedly expected to insert ASML's 1700i scanners.

TSMC's R&D researchers have resolved the defect issues by developing a proprietary defect-reduction technique that, on initial tests, produced less than seven immersion-induced defects on many 300mm wafers, a defect density of 0.014cm2. Some wafers have yielded defects as low as three per wafer, or 0.006cm2.

This compares to several hundred thousand defects produced by a prototype immersion scanner without these proprietary techniques and significantly better than published champion data in double digits.

"Our goal is always zero defects," said Burn Lin, senior director of TSMC's micropatterning division, in a statement. "Recently, TSMC produced multiple test wafers with defects rates as low as three per waferbetter than any other immersion results to date, and comparable to the very best dry lithography results. With defect root causes understood, TSMC can now focus on throughput improvement for high-volume manufacturing."

- Mark LaPedus
EE Times




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