Processor solution suits 3G wireless infrastructure

Wintegra Inc. announced the general availability of the W-series single chip multi-protocol access processor for 3G infrastructure applications.

The W-series devices provide a multi-protocol processing element that aims to meet the needs of 3GPP release 4, 5 and 6 Iub transport interfaces in micro, macro and pico basestation (BTS) products. These new devices utilize Wintegra's internal packet processing engines and its proprietary hardware architecture, which features modified symmetric multi-processors.

The product is a single chip solution, integrating the interfaces required for either end of the transport link, and connecting the BTS with the basestation controller. On-chip time division multiplexed, UTOPIA/POS and Ethernet interfaces are included, which allows direct connection to any ATM, IMA or IP transport. The W-series processors can also support SDH/SONET channelized interfaces as required by the 3GPP standards.

The processors provide a mix of interfaces for the on-chip Iub transport connectivity, 8 or 16 E1/T1 interfaces (through external PHY), 1 or 2 multi-PHY UTOPIA/POS L2 ports, multiple 10/100/1000 Ethernets and the ability to handle up to 84/63 T1/E1 (STM-1/OC-3) channelized support.

The product also has the following features: provisions for scalable control path and datapath processing; data path protocol support including ATM-UNI, ATM-IMA, IPv4/IPv6, UDP/IP, PPP, ML-PPP, MC-PPP and PPP-Mux; validated RTOS support for VxWorks and Linux.