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PHY/Serdes device with EDC capability

Posted: 06 Mar 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Aeluros? CMOS? PHY? Serdes? Puma?

Aeluros Inc., a supplier of low-power CMOS based 10G PHY solutions, introduced its next-generation 10GbE PHY/Serdes devices with integrated electronic dispersion compensation (EDC) capability.

The Puma AEL1003 device provides full PCS, PMA and XGXS sub-layer functionality, retains the cost savings features of the previous generation of 10G PHY devices, and adds EDC functionality for 10GBASE-LRM compliance.

According to the company, the Puma AEL1003 provides a full implementation of the IEEE 802.3ae 10GbE PHY layer functionality, along with the EDC features to meet the IEEE 802.3aq specification for 10GBASE-LRM. The device also has a 4-lane 3.125Gbps XAUI system-side interface, with a 10G serial line-side interface appropriate for implementation within XENPAK/XPAK/X2 MSA-based optical modules.

The Puma AEL1003 device is XENPAK register-set compliant, supports the use of external DOM devices or microcontrollers, and includes integrated PRBS and packet-level test pattern generators and checkers for effective device and module built-in self test (BIST) functions.

Aeluros has also included a clock synthesizer into the AEL1003 that allows for operation with a 50MHz source. This feature, along with BIST functions for modules and small packaging, allows modules manufacturers to effectively lower costs by simplifying module design and testing, added the company.

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