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Actel infrastructure enables mixed-signal systems deployment

Posted: 13 Mar 2006 ?? ?Print Version ?Bookmark and Share

Keywords:M7AFS? Fusion? programmable system chip? Actel? CoreAI?

Actel Corp. unveiled an expanded design infrastructure in support of its single-chip M7AFS device, the ARM7-enabled version of the company's Fusion programmable system chip (PSC). Contents of the new infrastructure include the CoreAI (analog interface) IP core, and CoreConsole IP Deployment Platform (IDP) and Libero Integrated Design Environment (IDE). Actel aims to give designers the capability to implement the ARM7-enabled, mixed-signal FPGA for applications such as communications, automotive, industrial and consumer.

Actel's CoreAI IP block allows the CoreMP7 soft ARM7 processor core to interface with the analog resources on Actel's M7 Fusion devices through the Advanced Peripheral Bus (APB). The CoreAI offers A/D conversion controlled by CoreMP7 and an APB slave interface with 8bit or 16bit width and 14 maskable interrupt sources. Further, an internal clock divider in CoreAI generates an analog configuration mux clock, and an optional-read FIFO stores up to 256 A/D conversions.

CoreConsole 1.1 provides access to CoreAI through an integrated "IP vault" as well as to Actel's entire DirectCore IP library, full AHB multi-master support, software driver export and memory map generation, and free CoreMP7 subsystem IP block updates.

Libero 7.1 IDE Gold allows users to instantly begin implementing ARM7-enabled, mixed-signal FPGA designs up to one million system gates. Optimizations to Libero 7.1 include design support for the first device in the M7AFS family, the M7AFS600. Additionally, the SmartGen core generator tool within the Libero IDE enables the configuration of the analog capabilities of M7AFS devices accessible through CoreAI.

The ARM7-enabled Actel Fusion PSC is said to allow designers to integrate a range of functionality into a single device, including support for 12V analog I/O, up to 8Mbits of embedded flash memory, integrated ADC and up to 1.5M system gates of programmable logic fabric. Further, the PSCs aim to extend the core benefits of the company's flash FPGA technologylive at power-up, low power, practical firm-error immunity and security.

Actel's Core AI will be available for free in April. Also free, the CoreConsole 1.1 IDP and Libero 7.1 IDE Gold will be available in April for download via Actel's Website. A Platinum edition of Libero 7.1 IDE is available for $2,495. All editions are one-year renewable licenses.

The M7AFS family includes four devices of varying gate densities, levels of embedded flash and analog channels. Samples of the M7AFS600 device will be available in April, with the M7AFS1500 sampling in 2H 2006. Implementation of CoreMP7 in Actel's ARM7-enabled Fusion devices starts below $5 in 250,000-unit volumes.

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