Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Primitive tools slow analog/digital integration

Posted: 16 Mar 2006 ?? ?Print Version ?Bookmark and Share

Keywords:bernard cole? john kusching? qualCore logic? jerry doorenbos? texas instruments?

Consumer demand for multimedia on small, low-power embedded and mobile devices is fast moving the industry into an era of billion-transistor SoCs. But there is a speed bump on the road to a smooth migration: the not-so-easy integration of analog/mixed-signal (AMS) circuitry with high-performance digital elements. Unlike digital circuits, in which the latest EDA tool methodologies can be used, AMS designs operate by much different rules. Going to smaller geometries not only fails to yield better analog performanceit sometimes lessens it.

High performance in SoC designs requires much more attention to the details of the design; less automatic routing, placement and other automation; and more handcrafting of the transistors and associated resistive and capacitive elements.

"The modeling and simulation needs for AMS transistors in SoC designs are much more critical and harder to achieve, and will take a while to resolve," said John Kusching, VP of engineering at QualCore Logic Inc.

Each move to tighter geometries has been a problem for analog designs. "So when you see digital designers pushing for 90-, 60- and 45nm as fast as possible, you will also see a lot of reluctance from companies developing embedded designs in consumer and mobile electronics, which require a lot more analog functionality," he said.

Leakage problems
Kusching also pointed out that "developing a high-performance, GHz-level mixed-signal device, such as a phase-locked loop at 90nm, results in leakage current problems as much as two to three times that of a few generations back. Leakages at that level make MOSFET capacitorsa staple of analog designact like resistors in parallel." Still another problem is simulation times. As far as they go, Spice simulators are essential in analog/linear design.

In SoCs, the designer must always be ready to accept compromise, according to Jerry Doorenbos, design engineering manager at Texas Instruments Inc.'s high-performance linear group. If none presents itself, the engineer must find a digital workaround that makes it possible to work with analog functions that are not precisely those needed. "If you absolutely need the analog functionality and the performance," he said, "either isolate that particular function and create an additional external circuit, or create two SoCsone with all of the analog functions aggregated and another with the digital."

However, with the right tools to help specify exactly which linear mixed-signal functions are necessary, the job of integrating high-performance analog and digital circuits on the same SoC should be easier. "Rather than having to design a circuit that must fit a broad range of capabilities, the developer can focus on those parameters of the most importance, optimize them and make compromises on the rest," Doorenbos said.

Incorporating extra digital functions that could eliminate the need for linear functions will help "deal with the compromises that have to be made on such things as accuracy, offset and gain errors, background and in-system calibration, allowing us to reduce the amount of analog," he said.

Although Spice simulators and analog modeling techniques from the large EDA vendors have improved steadily, they still leave something to be desired, especially as SoCs move down to 90nm and below, said Ross Hirschi, director of the Design Environment, Technology Solutions Organization at freescale semiconductor Inc.

"It may get even worse as we move down to tighter geometries," he said. "Every step forward taken with Spice simulation accuracy and speed is offset by the larger set of variables that have to be considered as fabrication technology edges closer to quantum limits. And despite improvements in EDA tools, they are not keeping up with increases in the number of parameters that must be considered in advanced designs."

Not only is this costly in terms of device characterization, but it hits hard during simulation in terms of time and in the amount of computing resources that must be thrown at the problem.

System level
deepak shankar, president and CEO of Mirabilis Design Inc., thinks more work is required at the system level, where high-level functional blocks are laid out. "And beyond more productivity-enhancing tools at the gate and transistor level, customers have been telling us there is a need for a way for digital designers to specify to the analog designers in a white-board sort of way the specific analog functionality needed," he said.

The more specific such directions are, "the more leeway it gives the designers of the AMS blocks," Shankar added.

Language support
At the transistor level, more capable analog modeling tools are coming into wider use. The emergence of standards such as the AMS modeling-language extensions to standard Verilog and VHDL holds a lot of promise, said Daniel Lee, technical-marketing engineer at Mentor Graphics Corp. Verilog-A (or Verilog-AMS) allows a developer to draw a sub-circuit with the definitions of how to compute the sources and impedances in that topology. From that input, a computable model is extracted. VHDL-AMS, on the other hand, bases its analog modeling format on writing simultaneous equations.

While AMS extensions will not necessarily speed up Spice simulations, they enable more selective use of Spice. Furthermore, they give the designer the ability to model a transistor, or a group of transistors, and create a mathematical model that approximates the performance. The trade-off is that AMS models are more abstract and do not cover all of the second-, third- and fourth-order effects found in an actual circuit schematic.

From the point of view of some digital designers, as SoC designs move above 1GHz, digital circuitry will become problematic, less predictable and harder to simulate. Also, at 90nm and 65 nm, critical effects like IR drop and device reliability must be analyzed at the transistor level.

- Bernard Cole
EE Times




Article Comments - Primitive tools slow analog/digital ...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top