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Verifying mixed-signal designs

Posted: 16 Mar 2006 ?? ?Print Version ?Bookmark and Share

Keywords:ken kumbert? henry chang? designer's guide consulting? mixed-signal design? top-down design?

The challenge of mixed-signal design differs in character from that of digital design. In digital design, the overwhelming challenge stems from the large size of the circuits. At the level of individual gates, the challenges are not demandingit's just that there are so many gates that the aggregate challenge is huge.

This is the reason why design automation is important. Only by automating the process of digital design does it become tractable on the very large designs that are common today. This issue has given rise to the infamous EDA gapan ever-widening chasm between the number of components that can fit on a chip and the capacity of the design tools.

With mixed-signal design, the challenge is less the size of the design (although it is contributing more each day) than the sheer difficulty of achieving the needed performance. In a mixed-signal design, each piece presents unique and difficult problems. They can be solved only by producing a custom circuit that fits the requirements of its particular situation.

The EDA industry has missed this point. For the past 10 years, companies have been trying to automate the mixed-signal design process, but automating it prevents designers from injecting substantial creativity.

Top-down approach
The traditional approach to design is referred to as bottom-up design. Once verified individually, individual blocks are combined and verified togetherbut at this point, the entire system is represented at the transistor level.

Design teams are increasingly implementing top-down design where the architecture of the chip is defined as a block diagram and is simulated and optimized using a system simulator such as Matlab or Simulink. These design groups have added a discontinuity to the design flow because the representation used during the architectural-exploration phase is incompatible with the one used during implementation.

A top-down verification process layers a formal modeling and verification methodology onto a top-down design process. Top-down verification methodically proceeds from architecture- to transistor-level design. Each level is fully verified before proceeding to the next and each level is leveraged in verification of the next. The process also formalizes and improves communications among designers. The formal nature of the communication allows designers to be located at different sites and remain effective.

Without analog synthesis, analog design is done the old-fashioned way, with designers manually converting specifications to circuits. While this allows for more creativity and gives higher performance, it also results in more errorsparticularly those that stem from miscommunication.

To overcome this problem, mixed-level simulation is used as a critical component of top-down design verification for analog and mixed-signal circuits. This represents a significant but essential departure from a digital design methodology. Mixed-level simulation is required to establish that the blocks function as designed in the overall system.

The pin-accurate system description, executed at a high level, acts as a testbench for the block, which is described at the transistor level. Thus, the block is verified in the context of the system, making it easy to see the effect of imperfections in the block on the overall performance of the system.

Typically, the top-level model is described in Verilog-HDL. In this way, the model can be shared with the people designing the larger digital portion of a chip. It can also be simulated within the mixed-signal design team with a Verilog-AMS simulator, which enables the mixed-level simulation because the individual blocks can be replaced with Verilog-AMS models, Verilog-A models or transistor-level netlists.

- Ken Kundert and Henry Chang
Designer's Guide Consulting




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