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Rx: New test techniques

Posted: 16 Mar 2006 ?? ?Print Version ?Bookmark and Share

Keywords:peter hulbert? keithley instruments? RF testing? DC testing? via stress migration?

As IC makers migrate to 65nm technology and look beyond this node, significant measurement challenges are emerging. Process development engineers must leave the well-behaved world of the Si/SiO2/polysilicon/Al materials system and immerse themselves in the challenging world of SiGe, silicon-on-insulator (SOI), HfNO2, metal gate, low-k and Cu materials. These new materials demand new measurements for process and device characterization. Some crucial applications include advanced high-k gate measurements, on-wafer RF s-parameter measurements, isothermal DC and RF testing of SOI substrates, and measuring leakage currents down to the femtoamp level.

Thus, traditional methods of DC testing no longer provide accurate models for device performance and reliability. Now, actual RF and pulse testing are requiredall the way from modeling to manufacturing. This includes measurements to determine gate dielectric reliability, high-frequency capacitance, copper via reliability and RF performance. Test methodologies are changing I-V characterization, RF capacitance-voltage measurement, s-parameters, NBTI, TDDB, HCI, SILC and charge pumping (CP).

These new approaches call for new instrumentation and software that take more measurements faster. At the same time, tests must be set up in a way that shortens time-to-market and assures long-term reliability of new products.

? More on-wafer measurements that uncover problems in front-end-of-line (FEOL) processes. A key FEOL qualification task is establishing product reliability associated with specific processes, particularly those involving new or exotic materials.
? Look for test equipment and techniques for advanced CMOS technologies. One example is a better way to characterize via stress migration (VSM) during relaxation of thermal stress, which gets better results in one-fourth the time of a 50hr isothermal test. The new technique cycles temperature through the region of largest creep rate and tracks small resistance shifts to improve failure statistics.
? Pulsed DC stress testing to acquire more diverse data and a better understanding of dynamic phenomena and device performance in frequency-dependent circuits. In particular, short-pulse measurements overcome gate leakage and provide an accurate picture of interface trap density in charge-trapping (CT) measurements.
? Select test systems with short-pulse capabilities and software that embraces newer test methodologies. These systems should be capable of supplying both DC and pulse signals with ns rise times to a small number of pins, without using a switch matrix.
? Select parametric test systems that have been designed specifically for high-throughput RF testing. Newer designs make fast, accurate and repeatable RF parameter extraction almost as easy as DC testing and can even take precise DC and RF measurements simultaneously.

? Limit testing to static DC measurements. AC and pulsed DC testing are needed for accurate CT measurements to qualify high-k gate dielectrics. Dynamic stress-measure techniques, such as charge pumping, are also valuable in characterizing reliability issues associated with NBTI, TDDB, HCI and SILC.
? Shy away from wafer-level RF parametric testing. Fabs now concede that RF s-parameter measurements are critical in building advanced ICs. Accurate RF parameter extraction at 1-40GHz has become essential for RF compact model verification as the industry moves to 65nm and beyond.
? Rely so heavily on end-of-line reliability testing. Testing packaged devices can obscure some reliability issues you are trying to uncover. It also involves significant costs and delays of up to three weeks associated with packaging.
? Get stuck in a routine of doing the same old tests, the same old way, with the same old test-system designs. Consider, for example, the change from Al to Cu metallization, which has opened the door to new testing needs and possibilities in areas such as VSM and parametric wafer-probing protocols.
? Use the same organizational and reporting structure for parametric and functional testingthe economics of the two are different. Parametric testing uses a sampling strategy for process control and yield improvement, and should be evaluated differently.

- Peter Hulbert
Semiconductor Industry Consultant
Keithley Instruments Inc.

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