Loop-timed SerDes offers low-power, high-speed

Analog Devices Inc. has developed a loop-timed serializer-deserializer (SerDes) device for passive optical networking (PON) terminals. Dubbed the ADN2865, the SerDes supports data rates from 12.3Mbps to 2.7Gbps, and consumes less than 1W of power.

The ADN2865 is said to be the industry's first SerDes to use a loop-timed architecture optimized for PON optical network terminals (ONTs). ADI's patented dual-loop clock and data recovery CDR architecture improves jitter performance, which is said to exceed the SONET specifications by a factor of three in all categories (jitter generation, jitter tolerance, jitter transfer.)

The device supports all data rates for Gigabit PON (GPON), Ethernet PON (EPON) and Broadband PON (BPON) and is designed to interface with the market's least-expensive FPGAs.

The ADN2865 is also said to be the first SerDes to offer fixed latency, a feature that allows system vendors to maximize throughput and control over their PON systems. The ADN2865 also features an optional bypassable limiting amplifier.

The ADN2865 SerDes is available in production quantities now and packaged in an 8 mm 8 mm LFCSP (lead frame chip-scale package). Pricing information is not available.

- Ismini Scouras
eeProductCenter