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Xilinx releases Virtex-4 FPGA based DDR2 reference design

Posted: 16 Mar 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Xilinx? Virtex-4 FPGA based 667Mbps DDR2? 667 DDR2-SDRAM? ChipSync? Micron?

Xilinx Inc. announced the immediate availability of the Virtex-4 FPGA based 667Mbps DDR2 reference design delivering high bandwidth and reliable memory interface solution.

The Xilinx 667 DDR2-SDRAM interface uses the innovative Virtex-4 ChipSync technology, a run-time calibration circuit that significantly improves design margins and overall system reliability while reducing design cycles, the company said. ChipSync technology simplifies the implementation of memory interfaces by compensating for routing, process, temperature, and voltage variations that produce skew between data and clock signals that may not be correctly estimated at design time.

The combination of Virtex-4 advanced silicon features, hardware proven reference designs and the easy-to-use Xilinx Memory Interface Generator tool provides the ultimate in design flexibility and reliability. Xilinx memory solutions are verified in hardware using memory devices from industry leaders like Micron and Samsung, including the new 667Mbps DDR2 reference design.

"Xilinx and Micron share a common objective to validate and provide market-leading memory solutions for a wide variety of applications from lowest cost to highest-performance," said Terry Lee, executive director of advanced technology and strategic marketing for Micron's system memory group.

"The Virtex-4 memory interface solutions enable system designers to build highly flexible, high bandwidth memory systems resulting in more competitive and robust end products," said M. H. Kim, director, technical marketing at Samsung Semiconductor.

The user-friendly Memory Interface Generator software tool supports any device/package combination, providing system designers with the additional flexibility to easily customize their design. The reference designs, available in Verilog or VHDL, use a modular approach to provide distinct physical layer, user interface and controller blocks.




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