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Synopsys claims first complete SystemVerilog flow

Posted: 22 Mar 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Dylan McGrath? Synopsys? SystemVerilog?

Synopsys Inc. laid claim to being the first EDA vendor to provide a complete SystemVerilog flow, saying the language is now supported throughout its suite of design and verification products.

According to the company, more than 150 companies are already using its SystemVerilog solutions in design and verification. Steve Smith, senior director of platform marketing for Synopsys' verification group, said the company expects the availability of a complete SystemVerilog flow to dramatically increase the number of companies using SystemVerilog.

SystemVerilog, which was approved as a standard by IEEE last November, is said to express complex designs more succinctly and accurately, enabling designers to capture critical design attributes with assertions and develop advanced coverage-driven, constrained-random testbenches. A survey conducted by moderator John Cooley last year found that 44 percent of 338 respondents planed to use SystemVerilog within the next year.

Synopsys products supporting the SystemVerilog standard now span the Galaxy Design and Discovery verification platforms, including Design Compiler for logic synthesis, the VCS comprehensive verification solution with Native Testbench, the Pioneer-NTB SystemVerilog testbench automation tool, the Formality equivalence checker, the Magellan hybrid formal analysis tool, and the Leda programmable RTL checker, Synopsys said.

According to Smith, early adopters of SystemVerilog have been using the language through multi-vendor flows of point tools cobbled together, sometimes painstakingly. The availability of a cohesive, integrated flow will spur more companies to employ the language, Smith said.

- Dylan McGrath
EE Times

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