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New line of ZenTime products addresses specific cell design issues

Posted: 30 Mar 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Zenasis? ZenTime? cell design? cell-based design? standard cell design?

Zenasis Technologies unveiled three new members of its expanded ZenTime product familyZenTime-GT, -AT and -PT, which automate standard cell design optimization for timing, area and leakage power, respectively.

"During the optimization implementation phase of any chip design, people are struggling to balance power, performance and other issues," said Zenasis CTO and co-founder Jay Roy. "Timing closure, leakage power, and IP core integration and migration are some of the issues in standard cell design."

By utilizing Zenasis' patented hybrid optimization technology to analyze and optimize standard cell designs at the logical, physical and transistor levels, said the press release, the ZenTime products achieve many of the benefits of custom design in a manner transparent to the designer.

"Hybrid optimization makes it possible to simultaneously look at the active trade-offs between power, timing and die size. We are offering a combined solution that can trade-off power and timing simultaneously under the same hood," added Roy.

New family members
ZenTime-GT, the timing optimization tool, enables designers to stay in their current process technologies and delay the move to smaller and lower-yield processes. It uses timing optimization techniques, including buffer tree construction and restructuring, gate sizing with existing standard cells, pin permutation, inverted logic gates, and output stage sizing. It is integrated with placement and static timing analysis engines and can be plugged directly into existing standard cell design flows.

"You probably spend half of your design cycle to solve the problems in the last 10 or 20 percent," Roy explained. "With our technology, you can get those things up front. Its a huge savings in terms of time-to-market, and that has been a benefit."

ZenTime-AT, the product familys area optimization application, reduces die size; hence, decreasing product cost as well. It works in conjunction with ZenTime-GT to manage the area trade-offs that can be associated with meeting timing constraints, and recovers area affected by timing optimization and positive slack points.

Meanwhile, ZenTime-PT, the product familys leakage power optimization application, operates in multi-Vt or single Vt design flows. It reduces leakage power on the non-critical paths, and enables efficient use of low-Vt cells in a multi-Vt design, resulting in longer battery life.

The ZenTime family now includes ZenTime-GT, ZenTime-AT, ZenTime-PT and ZenTime-XT (formerly ZenTime). This product family runs on Linux and Sun-Solaris platforms.

New market
While ZenTime-XT, which was released in 2003, was targeted for IDMs, the three new ZenTime family members have a different market. "We are looking at proliferating our technology to the mainstream," Roy said. "In an effort to do that, we found out that we could carve out few of the pieces of ZenTime in terms of the optimization capabilities. That would enable us to target the fabless market, which is a bigger one."

Roy also disclosed Zenasis' plan to expand its presence in Asia. The company presently has offices in Korea and Japan, and distributors in Taiwan. "We have just hired another distributor in Taiwan, and we are presently setting up operations in India."

- Tracy Carpena
Electronic Engineering Times-Asia

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