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Aldec offers 90-day free access to Riviera Verilog simulator

Posted: 31 Mar 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Aldec? EDA? simulation? Riviera? UltraSPARC?

Aldec Inc., an EDA tool provider, announced yesterday full simulation support in Riviera for the open-source UltraSPARC T1 from Sun Microsystems.

Riviera, a mixed language Hardware Description Languages (HDL) simulator, supports common kernel simulation of complex digital logic circuit designs that have been written in HDL, including VHDL, Verilog, SystemVerilog and SystemC.

"Aldec looks forward to the many new possibilities and applications that the OpenSPARC community will develop. We are offering the utilization of Aldec's Sun Solaris based Riviera simulator at no cost for 90 days to all qualified organizations that drive the art and science of multi-core, multi-threaded hardware and software design," said David Rinehart, vice president of marketing at Aldec.

Sun has released its UltraSPARC T1 multi-core processor to the general public. Sun's initiative will allow the OpenSPARC community to implement custom logic circuit hardware designs using the OpenSPARC T1 Verilog source code model of the UltraSPARC T1. To support this effort, Aldec will offer free access to its Riviera Verilog simulator on the Sun Solaris 10 platform for a 90-day trial basis to all qualified organizations. The Riviera trial license is available from the OpenSPARC community website.

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