Virtex-4 FPGAs turn into traffic managers for triple-play apps

Xilinx has partnered with Modelware Inc. to provide designers of networking infrastructure equipment with a product that will enable them to integrate advanced traffic management features into their systems. With the ability to support throughput from 50Mbps to more than 10Gbps, the hardware-based product can manage traffic in all types of triple-play applications from access equipment to metro core routers.

Traffic management is not a new market for Xilinx, but the FPGA maker has recently seen growing demand for quality of service (QoS) products as voice, data and video (also known as triple-play services) increasingly converge over one network. The intent is to provide a seamless wired to wireless infrastructure with IP as the unifying protocol.

Approximately 62 percent of firms surveyed by Economist Intelligence Unit expect to have migrated to converged IP networks across all or most of their businesses in three years. The key block that is required is traffic management, which includes functions like policing, shaping, congestion avoidance and management algorithms. The goal is to guarantee QoS, support different classes of service (CoS) and enforce service level agreements (SLA).

"You're starting to see the convergence of IP multimedia systems," said Delfin Rodillas, staff system architect, wired communications, Xilinx. "The drivers have been the same for the last several years on the consumer side, broadband services and IP infrastructure. For service providers, they are looking for new revenue streams and a way to reduce capital expenditures. We are keyed in on this trend."

Indeed, Xilinx has partnered with Modelware, a provider of Semiconductor Intellectual Property (SIP) cores for telecom and networking ASIC and FPGA applications, to provide makers of networking infrastructure equipment with hardware-based traffic management products that are higher performing, as well as more scalable and flexible than network processors, ASICs and packet-processing chips. Traffic manager manages the flow of multimedia traffic and helps prioritize data in a system.

The traffic manager product is based on Xilinx's Virtex-4 FPGAs, and provides a very scalable set of parameters, which include up to 1.2 million queues, up to five scheduling levels, and up to 64K multicast groups. The memory architecture can also be scaled down to 50-Mbits/s for lower-rate access applications like PON OLTs or beefed up for metro access applications such as metro core routers that require 10Gbps bandwidth.

Xilinx realizes that its products must provide high integration and optimization to meet various cost points since a high-end FPGA may work for a Metro headend application, but not for IP DSLAM.

"Traffic management is different across customers—everyone has their own recipe. Many companies consider traffic management their secret sauce, so they want to make sure that they can implement their traffic management requirements as it and without compromise to performance and functionality," he said.

A design is optimized to a customer's specifications; Xilinx will provide an FPGA that's just right for the traffic manager. For example, in an access equipment design, the traffic manager may be using a smaller density LX40 Virtex-4 FPGA. For a metro equipment application, traffic manager may use an LX100 Virtex-4. The design scales; it's not fixed to one size FPGA or another. Designers also have the opportunity to integrate other functions in the FPGA. Another example: if the user is going to connect the traffic manager to a backplane, the FPGA might integrate an XAUI interface. In that case, an FX device would be used since it has an embedded SerDes.

"Traffic manager can be combined with custom logic, integrated PowerPC processor and multi-gigabit transceivers to reduce the total BOM," he said. "All of these factors together ensure that you get the most cost-efficient size traffic manager available."

- Ismini Scouras
eeProductCenter