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Serial RapidIO IP core available for Virtex, Spartan FPGAs

Posted: 03 Apr 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Serial RapidIO IP core? FPGA? field-programmable gate array? Mercury Computer Systems? Clive Maxfield?

Mercury Computer Systems has joined the Xilinx Alliance Program. Mercury also announced the availability of a new Mercury Serial RapidIO IP core for Xilinx Virtex and Spartan FPGA families.

The Xilinx Alliance Program is said to be composed of companies with the best available technologies in the areas of IP cores, EDA, DSP and embedded development tools, as well as design services, board-level products, integrated circuits and electronic components. Member companies provide optimized products and services that contribute to a broad selection of solutions dedicated for use with Xilinx programmable logic.

The new Serial RapidIO offering is a full-featured, high-function IP core that incorporates a logical layer, a transport layer and a physical layer, and supports I/O and message passing.

Compliant with the Serial RapidIO specification 1.2, the Mercury IP core targets applications for embedded, communications, wireless, storage and defense markets. Designers using Xilinx Virtex FPGAs can incorporate Mercury's IP to create devices with a robust Serial RapidIO endpoint for a variety of applications.

Mercury's IP has been successfully integrated into multiple Xilinx components with either an internal or external Serdes device, and can also be used to create multi-port switches to aggregate other Serial RapidIO inputs. Xilinx multi-gigabit transceivers offer core interface speeds of 4 x 3.125Gbps.

- Clive Maxfield
Programmable Logic DesignLine

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