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4Gbit NAND adds error correction code

Posted: 03 Apr 2006 ?? ?Print Version ?Bookmark and Share

Keywords:BCH error correction code? NAND flash? STMicroelectronics? David Lammers?

STMicroelectronics is adding complex, on-chip BCH error correction code (ECC) technology to a 4Gbit NAND flash memory chip that's coming to market soon.

Error correction is increasingly important as NAND chips begin to play a dual rolestoring code and data. Bits that are lost in an MP3 audio file are usually inconsequential; bits lost as the phone tries to boot up result in a dead line.

At the recent International Solid-State Circuits Conference in California, ST presented work on its 2bits/cell architecture, which departs from the more conventional error-correction techniques to incorporate the Bose-Chaudhuri-Hocquenghem (BCH) algorithm.

Giulio Casagrande, director of research and development at ST's memory products group, said many customers put error correction on the memory controller, but that requires knowledge of ECC techniques, and BCH is difficult. "BCH ECC is almost transparent to the customer when you put it on-chip. And the 1.3mm2 size for the ECC block is very good," he said.

Rino Micheloni, multilevel-NAND development manager, said error correction for the single-level-cell NAND chips "is quite easy to do. If you consider multilevel-cell NAND, you might imagine it only doubles the complexity. But, in fact, error correction is about a thousand times more complex."

The BCH correction scheme is "too difficult" for many customers to implement at the system level, Micheloni said, making the on-chip approach more viable, especially for multilevel-cell (MLC) parts. Putting ECC in the controller can also result in a steep penalty in terms of read throughput. ST's 4Gbit MLC NAND chip is capable of 40MBps read throughput, he added.

STMicroelectronics is working to increase its NAND flash business, which accounted for $89 million in revenue in Q4 of 2005, about 2.5 percent of the overall NAND market, according to market research firm iSuppli Corp. ST will roughly double its capacity this year, iSuppli predicts, to 55 million 512Mbit equivalents by the fourth quarter. Samsung dominates the market with a 50 percent share, followed by Toshiba Corp. and fast-growing Hynix Semiconductor Inc.

China ramp
Casagrande said that ST and Hynix forged a NAND technology and design alliance three years ago, which includes capacity-sharing at a new 300mm wafer fab in Wuxi, China, two hours outside of Shanghai. The 4Gbit NAND chip, which is sampling now, will be made initially in Singapore and then ramped up in Wuxi.

"For sure, 2bits/cell is in the minority now, but everybody is putting a priority on it and we think it will be in the majority in one or two years," Casagrande said. "NAND will undergo the same transition that NOR went throughnow, all the 128Mbit and 512Mbit NOR parts are 2bits/cell."

- David Lammers
EE Times

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