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FPGAs consumed by power issues

Posted: 03 Apr 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Richard Goering? Power? FPGA 2006 symposium? power consumption?

Power issues charged up the recent FPGA 2006 symposium, and for good reason!many observers see high power consumption as perhaps the biggest factor limiting wider usage of the devices.

It's technically feasible to build an FPGA for mobile, battery-powered applications, said a Xilinx Inc. researcher at this research-oriented conference. But finding the right balance between power reduction and the trade-offs it brings is challenging, participants said. At an evening panel discussion titled "Will power kill FPGAs?," no one disagreed that ASICs still hold an overwhelming power advantage over FPGAs.

The Xilinx paper, presented by researcher Tim Tuan, described a research project in which Xilinx built a low-power architecture based on the company's Spartan 3 fabric. Applying such optimizations as voltage scaling, power gating, low-leakage configuration memory and sleep mode, the resulting Pika architecture is said to produce 46 percent less active power and 99 percent less standby power than the baseline Spartan 3!at the expense of a 27 percent performance loss and 40 percent area penalty.

"Power consumption is clearly the No. 1 factor holding up FPGAs from penetrating the vast majority of consumer applications," noted Bryan Lewis, analyst at Gartner Dataquest. "If these [Xilinx] low-power claims can be met in volume production, this could provide a significant upside to the future FPGA market."

But are the performance and area trade-offs worth it? If not, the conference revealed more modest approaches, such as a technique currently used in Altera Corp.'s Quartus tool for power-aware mapping of embedded RAM blocks. As described by researchers from Altera and the University of Massachusetts, that approach reduces memory dynamic power by 21 percent and overall dynamic power by 7 percent, at just a 1 percent cost in performance and logic.

Designers have long known that FPGAs have far worse power consumption than ASICs, but quantification has been lacking. A paper presented by Ian Kuon, PhD student at the University of Toronto, showed just how large the gap can be. The authors used a broad series of RTL benchmarks to compare a 90nm Altera Stratix II implementation to a 90nm CMOS standard-cell ASIC implementation from STMicroelectronics. Tool flows included synthesis, placement and routing.

Dynamic power, the researchers found, was on average 12 times worse for the Stratix FPGA over the range of benchmarks. It didn't matter much whether simulation or a toggle test was used to compute the results. The gap narrowed slightly with hard blocks on the FPGA.

Static power presented a more complex picture. Here, said Kuon, the gap ranged from 5.4x to 87x worse for the FPGA, depending on process, voltage and temperature conditions!making it impossible to come up with a reliable measurement. The paper also said that area was on average 40x worse and delay 2-5x worse for the FPGA implementation.

Xilinx's Tuan noted that low standby power is crucial for mobile applications and that ICs for such applications ideally dissipate less than 1mA. But FPGAs may dissipate 10-500mA, he noted. Pika claims to close that gap and bring FPGAs into an acceptable range for mobile, battery-powered products.

Research phase
Tuan emphasized that Pika is a research project only!it does not indicate that a future product will be forthcoming from Xilinx. As he acknowledged, it has yet to be determined whether the architecture's added area and cost would result in substantial marketplace demand.

In the Xilinx paper, "active" power refers to both dynamic and leakage power when the circuit is running. "Standby" power refers to leakage power when the circuit is idle. In the Spartan 3, Tuan said, routing accounts for about 62 percent of the active power and 36 percent of the static power. The larger factor in static power is configuration SRAM, which accounts for 44 percent.

One technique used by Pika is voltage scaling. Researchers chose 1V as a core operating voltage. This, said Tuan, resulted in a 30 percent reduction in active power and a 40 percent reduction in standby power, with a 15 percent performance penalty.

The Xilinx research team found that leakage from configuration SRAM could be significantly reduced by using midoxide, high-Vt transistors. This is possible, Tuan said, because configuration memory doesn't switch during normal operation and can thus run more slowly. The result: SRAM leakage was reduced by two orders of magnitude with no performance loss.

Pika also makes extensive use of power gating, which uses power transistors as headers or footers to cut off leakage from unused blocks. One issue to resolve is granularity and Xilinx decided to apply power gating at the individual tile level (a tile consists of a configurable logic block plus its routing). Using midoxide power gates, the architecture achieved a 10x leakage reduction in exchange for 10 percent performance degradation.

Finally, Pika offers a "sleep" mode that is activated by a dedicated user pin and can disable all power gates. A partial sleep mode lets users define any configuration of tiles to remain active. Configuration memory retains the necessary circuit states and Pika wakes up from standby mode in about100ns.

One advantage of the Pika approach, Tuan said, is that it uses existing EDA tools and flows. He expressed confidence that the 40 percent area penalty can be lowered with better floorplanning and routing.

"Everything they [Xilinx] talked about can be built," commented Vaughn Betz, director of Altera's Toronto Technology Group. "They're using recognized techniques that are well-known in the semiconductor industry. Whether it's doable economically is the big question."

While it's possible to cut leakage power dramatically, Betz said, dynamic power is a much tougher nut to crack. He said that FPGAs for battery-powered applications will have to remain small or they'll burn too much dynamic power. And small FPGAs, he noted, don't bring in a lot of revenue.

Altera, Betz said, offers power optimization in its Quartus software and supports various types of power gating. One optimization technique used by Quartus is to minimize the number of RAMs that are active during clock cycles. The technology behind it was described in the paper given by Altera and the University of Massachusetts. It described a set of power-aware, logical-to-physical RAM mapping algorithms that can minimize RAM dynamic power by choosing the best possible mapping. The authors note that the best way to minimize embedded-memory dynamic power is to disable the clock-enable signal when memory port access is not required. Optimization thus seeks to minimize dynamic activity through the effective use of RAM port clock enables.

A paper from the University of British Columbia, meanwhile, examined the trade-offs among flexibility, area and power in FPGA clock networks. PhD student Julien Lamoureux noted that FPGA clock networks significantly impact power because they toggle at every clock cycle.

The paper described a parameterized clock network, along with experiments that compared flexibility, area and power. One conclusion: Power depends on how many clocks are being used, not on how many clock resources exist in the circuit. Another conclusion is that increasing the clock regions generally cuts area and power.

One power-reduction technique FPGA researchers ought to think about, said Jason Cong, chairman of the computer science department at the University of California at Los Angeles, is multiple voltage islands under programmable control.

At the evening panel discussion, two panelists argued that FPGAs will remain far behind ASICs in power consumption. "FPGAs are about 20 times more power-hungry than ASICs, and this will not improve with scaling," said Zeev Wurman, staff scientist at eASIC. "Whatever an FPGA can do to reduce power, an ASIC can do better."

Gary Delp, distinguished engineer at LSI Logic Corp., noted that FPGAs have 10-100x the routing capacitance of an ASIC, larger routing tracks and large numbers of transistors that aren't used in circuit operation, but still contribute to leakage.

"If you need the lowest power, you should use a custom design or ASIC," said Xilinx's Tuan. "But if you want programmability, FPGAs are the most energy-efficient programmable solution."

Betz echoed that point when he said FPGAs have better power efficiency than DSPs or processors.

"Power optimization in FPGAs is just beginning," Tuan said. "The reason we don't have low-power FPGAs is not because it can't be done, but because the market hasn't demanded it."

Above 90nm, Betz said, FPGAs were not scaled for power. "That changed at 90nm and will never change back. We are now in a world of power-constrained scaling." This means that a device with 2x the capacity will dissipate the same power, he said.

UC Berkeley professor Jan Rabaey noted that many techniques for reducing power are done more easily in regular fabrics. "I believe FPGAs may be the solution to the power problem," he said.

- Richard Goering
EE Times

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