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Vendors warm to SystemVerilog

Posted: 17 Apr 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Richard Goering? Synthesis tool? SystemVerilog? RTL? Synopsys?

Synthesis tools are beginning to support SystemVerilog, but there's a probleman RTL model that runs in one synthesis tool might not run in another. A proposed standard SystemVerilog synthesis subset is getting good reviews from most synthesis providers, albeit with some skepticism from market leader Synopsys Inc.

At the recent DVCon conference, Stuart Sutherland, president of training firm Sutherland HDL, presented a detailed proposal for a standard SystemVerilog synthesis subset. He said that the proposal came about from "trial and error" and suggestions from several synthesis providers.

"The key problem is that companies want to work with multiple vendors' tools, but they have a portability problem," he said. "They can't write code and have it work in different tools." Standard synthesis subsets exist for Verilog and VHDL, Sutherland noted, but not SystemVerilog.

While there's no formal standardization activity yet, synthesis vendors appear strongly supportive, except for the biggest one of all. "Synopsys is not opposed to the subset; we just don't see the demand for it," said Karen Bartleson, director of interoperability at Synopsys. "It doesn't make sense for the industry to spend valuable resources developing standards unless there is strong customer demand."

Cadence Design Systems Inc. has a different view. According to Victor Berman, group marketing director at Cadence, there is "certainly" a need for a synthesizable subset for SystemVerilog, even if it's an informal standard at this stage.

Cadence reviewed an early draft of Sutherland's proposal, Berman said. "I agreed with almost everything Sutherland said. A few features won't be implemented up front, unless customer demand for these features becomes apparent."

"Mentor Graphics fully supports a standardization effort for a synthesizable subset of SystemVerilog," said Daniel Platzker, product-line director for FPGA synthesis. While Mentor has defined its own synthesizable subset for its Precision FPGA synthesis tool, the company would like to see the Accellera standards organization charter a working group to develop a standard, he said.

"We like the Sutherland proposal and agree there should be a defined synthesizable subset specification for SystemVerilog," said Andrew Dauman, VP for corporate applications engineering at Synplicity Inc. "We would like to see this as an addendum to the IEEE 1800 SystemVerilog spec."

Comprehensive subset
Yatin Trivedi, director of product marketing at Magma Design Automation Inc., said that a standard synthesis subset is important for common interpretation and usage across the tool chainnot only synthesis, but also formal verification, power analysis, RTL prototyping and design-for-test generation. He said that Sutherland's proposal is "very comprehensive."

Startup Bluespec Inc., which offers synthesis from SystemVerilog assertions, views a synthesizable subset as "essential," said Rishiyur Nikhil. But there's a qualification. "One should be aware that tool implementations emphasize certain aspects of language over others," he said. "So, although designs are portable, they rarely port well."

Sutherland acknowledged that there can be a "least common denominator" phenomenon in which a subset only defines what everyone agrees to. But the alternative, he noted, is having features that are supported in only one tool, leading to a lack of portability.

Sutherland's proposal lists synthesizable SystemVerilog constructs, including various types of packages, variable data types, net data types, user-defined types, unions, data arrays, module ports, operators and procedural blocks.

Sutherland expects the most controversial issue to be packages, which are currently supported by some tools, but not others. Packages are valuable, he said, because they allow user-defined types that are shared by several modules. There are also synthesizable features that tools don't currently support, he said, such as queues and object-oriented programming.

One question is where a synthesizable subset will be defined. Sutherland thinks it would be a good project for the Accellera standards organization.

Accellera has not committed to any such effort. "If there is a need for revised SystemVerilog specifications among our constituents, our technical groups will look into this," said Shrenik Mehta, Accellera chairman.

- Richard Goering
EE Times




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