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Teranetics 10GbE chips run on X Architecture

Posted: 20 Apr 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Cadence Design Systems? Teranetics? 10GbE chip? 10GBASE-T? X Architecture?

Cadence Design Systems Inc. and Teranetics Inc. have announced a design collaboration for the implementation of Teranetics' 10GbE chips, the 10GBASE-T, using Cadence's X Architecture.

According to the press release, Cadence's X Architecture represents a new way of orienting a chip's microscopic interconnect wires with the pervasive use of diagonal routes, in addition to traditional right-angle "Manhattan" routing. The solution provides significant improvements in chip area, performance, power consumption and cost, by enabling designs with significantly less wirelength and fewer connectors between wiring layers.

The two companies said that its design collaboration leverages the significant reduction in power consumption enabled by the X Architecture. Reducing power consumption is a key requirement in the deployment of 10GBASE-T chips in data centers and enterprise networks.

"We are very excited with the remarkable reduction in power consumption demonstrated by the Cadence X Architecture design solution and plan to leverage it for our designs at advanced process nodes," said Teranetics CEO Sanjay Kasturia in a statement.

Teranetics also became the latest member of the X Initiative, a consortium of semiconductor industry design-chain members pushing for the acceleration of X Architecture fabrication and availability.




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