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Getting the right turn-on sequencing for hot-swap

Posted: 01 May 2006 ?? ?Print Version ?Bookmark and Share

Keywords:ON Semiconductor? power management? mezzanine card system? DC/DC converter? alex lara?

The introduction of the industry-standard Advanced Telecom Computing Architecture has spurred the development of new hardware platforms.

AdvancedMCTM specifications provide a standards-based architecture for a 12V mezzanine card power-management subsystem in next-generation communications equipment. Subsystem issuessuch as hot-swap and delivery of multiple point-of-load voltages in a single, size-constrained system environmentare creating important power-management challenges for mezzanine card system designers.

One challenge is the turn-on sequencing of different point-of-load voltages in a single card. Some applications may require turn-on of a specific point-of-load voltage before the others. For example, a computing card may contain several different point-of-load voltages for different needsmicroprocessor core, north bridge, south bridge, DDR2 memoryand they may need to be turned on in a specific sequence. If the DC/DC converter 1 (microprocessor core) has to be turned on before the DC/DC converter 4 (DDR2 memory), it is necessary to design a circuit that can provide hot-swap capability and turn-on sequencing at the same time. This can be a big design challenge for discrete hot-swap circuits, since these require a lot of external biasing components and major tweaks after implementation to make them work properly. Thus, a simpler and more reliable solution is definitely needed.

Using a hybrid solution such as the NIS5102 device simplifies the circuit design and implementation for hot-swapping and turn-on sequencing capabilities in AMC applications. This device also increases the whole system's reliability due to its unique internal thermal protection and active current-limit circuits.

The built-in active current-limiting and thermal-protection circuits of the NIS5102 devices provide hot-swapping capability for both DC/DC converters 1 and 4. The turn-on sequencing is made through the power-good signal of the NIS5102 device. By connecting the power-good signal of device 1 to the enable pin of device 2, the enable pin of the NIS5102 device 2 is kept low until device 1 has fully turned on. This way, the DC/DC converter 4 (DDR2 memory) will not be powered up until the DC/DC converter 1 (microprocessor) has been turned on. If a longer delay time is desired to turn on DC/DC converter 4, a bigger capacitor value connected between the enable pin and ground of the NIS5102 device 2 may be used.

- Alex Lara
Applications Engineer
ON Semiconductor Corp.

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