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Nvidia adopts Synopsys' topographical tech

Posted: 27 Apr 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Synopsys? NVIDIA? topographical technology? Design Compiler Ultra?

Synopsys Inc. announced that Nvidia Corp. is deploying the "topographical technology" in Synopsys' Design Compiler Ultra to increase the competitiveness and accelerate time-to-market for its next-generation designs.

According to the press release, the ability to accurately predict key characteristics of a design, such as timing and area, during the early stages of development allows Nvidia's designers to synthesize a better netlist for physical implementation. This results in significant productivity gains, fewer design iterations, and faster time-to-market, said Synopsys.

Dan Smith, director of hardware engineering at Nvidia, believes that Design Compiler's topographical technology is a better approach to synthesis since it "generates results that more closely correlate to physical implementation and therefore reduce iterations between synthesis and physical tools."

"The topographical technology fits readily into our design flow, delivering area and timing correlation which is within three to six percent of post-placement results. In addition, with this technology we are realizing reduced congestion," said Smith. "These results, complemented by the improvements we have seen in DC Ultra 2005.09, are driving our decision to deploy this technology on our next-generation designs."

The topographical technology in Design Compiler utilizes Synopsys' advanced placement and optimization algorithms to bring accurate timing and area context into the synthesis engine, eliminating synthesis dependency on wireload models. This results in very close timing and area correlation between synthesis and physical design, giving RTL designers early visibility into downstream design issues and eliminating costly iterations between synthesis and layout, said the company.




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