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Sidense to deliver OTP cores in UMC's 90nm, 65nm process nodes

Posted: 28 Apr 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Sidense? UMC? OTP core? United Microelectronics? 90nm?

Sidense Corp. and United Microelectronics Corp. (UMC) announced that Sidense's 1T-fuse family of embedded One-Time-Programmable (OTP) cores are slated to be silicon-verified in UMC 90nm and 65nm processes through UMC's IP Alliance Program and offered for use to SoC designers.

The cores are scalable to UMC's CMOS processes without requiring additional mask or processing steps, providing users with shortened time-to-market and a path to cost reduction for their current and future designs, said the press release.

Sidense's high density macros can also be parameterized to obtain different configurations and can be used to replace external FLASH and EEPROM as well as a field programmable alternative to MASK ROM.

"UMC's extensive IP portfolio has become a strong competitive advantage for customers designing today's sophisticated SoCs," said Ken Liou, director of the IP and design support division at UMC. "Sidense's technology is a welcome addition to our IP Alliance Program, as it will provide designers with a silicon-proven OTP option for their 130-, 90- and 65nm designs."

In January, Sidense announced its OTP core targeted towards UMC's 130nm standard logic digital CMOS process.

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