PLL solution verifies complete closed loop noise

Xpedion Design Systems Inc. announced GoldenGate, a transistor-level phase-locked loop (PLL) solution for verifying complete closed loop noise and jitter. This product seeks to assist PLL designers in verifying their designs prior to silicon to save design spins.

"We worked with Xpedion to successfully verify simulated results against measured data for our CMOS PLL with over 500 transistors operating at 622MHz, including the crystal oscillator and the integer divider," reveals Pierre Guebels, vice president of engineering at Phaselink Corp. "This capability is a tremendous step forward in verifying PLLs prior to tape-out."

GoldenGate is said to allow designers to view full noise contributions from all contributors, including the crystal oscillator, allowing designers to pinpoint and fix problems. Historically, this is done through an iterative process of respins.

Currently, Xpedion is engaging with existing customers on this technology through partnerships and service agreements.