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Chipworks inside TI's DLP chip

Posted: 01 May 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Dick James?

Texas Instruments (TI) started developing DLP (Digital Light Processor) MEMS products in 1987 and launched them in 1994. Since then, market acceptance has been growing at an increasing rate. Last December, TI announced shipment of the five millionth unit, up from three million in April 2004. Today, they must be closing in on ten million devices shipped.

TI seems to have settled on four main marketsrear projection TVs, and front projectors for home, business and cinema. The DLP system we examined came from a Dell 2300MP projector, together with the accompanying DAD1000 and DDP2000 controller ASICs.

The MEMS part of the DLP was actually the S1076-7402 XGA Digital Micromirror Device (DMD). This is a 0.7 inch-diagonal spatial light modulator, using a 1,024 x 768 array of aluminum micro-mirrors, fabricated over 5-transistor SRAM driver cells. The mirrors are grouped into 48 blocks, with each block containing 48 rows of 1,024 mirrors.

The drive circuitry is fabricated in a 0.6?m CMOS process using P-/P+ epitaxial substrates, which unfortunately we do not have space to look at here. The base wafers are fabbed either by TI or DongbuAnam, and Amkor has been reported as the packaging house.

The device is packaged in a solidly built hermetic glass/metal/ceramic assembly, complete with a substantial heat slug and internal getter strips (Figure 1). There is a rectangular window on the inside of the glass to limit light only to the mirror array, and 159 gold-coated contact pads on the base.

Figure 2 is a photo of the die after removal from the package. The device uses five layers of metal, three for the CMOS circuitry, and two for the MEMS superstructure. The purple areas around the edge of the die are metal 3 (M3), covered with a thin oxide tuned to give minimum light reflection, and used to screen the address circuitry. Our photo is stitched together from multiple images, which gives the mosaic effect in the picture.

A corner of the array is shown in Figure 3; the individual mirrors are 12.7?m2, on a 13.7?m pitch. The dark dot in the center of each mirror is the support post connecting it to the torsion hinge below. Figure 4 is an SEM image of the M5 mirrors, with two mirrors removed.

A closer view of the M4 under-mirror metal (Figure 5) shows the torsion hinge oriented diagonally, with the hinge support plates at the top right and lower left corners of the pixel, connected to the M3 underneath. This metal 3 line is connected to adjacent pixels at the left- and right-hand edges of the pixel, allowing the row of mirrors to be biased. The mirror address electrodes are on either side of the hinge, again connected to M3.

The M4 hinge layer and M5 mirror layer are both deposited and defined on sacrificial organic layers. It is not apparent in the SEM images, but the M3 in the array is also coated with the same thin oxide as the peripheral metal. This "dark metal" is used to prevent stray light from travelling to the screen when the mirrors are switched off. This is claimed to improve contrast ratios from 800:1 to >1,500:1.

The mirror electrodes are connected to the inverter outputs of an SRAM cell sited underneath each mirror (Figure 6). Over 12V is required to tilt the mirrors, so the 7.5V CMOS transistors in the SRAM cell are inadequate. To overcome this, a large bias voltage (up to 28V) is applied to the mirror bias bus. This, plus the mirror address electrode bias, provides the electrostatic forces needed to tilt the mirrors. Once the mirrors are latched, an opposite mirror bias is also used to force them to release.

The mirrors are latched and unlatched by binary data, and the grey level of each pixel is determined by the duty cycle of the mirrorthe greater the percentage of times the mirror is latched into projection position, the brighter the apparent intensity. The mirrors tilt 12 each way to differ between the projection path and the dark path for the incident light.

In Figure 7, we see a cross-section of the DLP structure, showing the three conventional CMOS metal levels, the thin (70nm) M4 torsion layer, and the M5 mirror metal. The aluminium mirror is optimized to have 90 percent reflectivity, and the torsion metal is an Al/Ti alloy, presumably tuned to have the right torsion and reliability characteristics. The M5 thins quite noticeably on the sidewalls of the contact to the hinge metal, and we can also see the M4 vias etched deeply into M3.

Figure 8 is a close-up TEM image of the mirror/hinge contact, and we can clearly see how thin the hinge is, but even so TI claims remarkable reliability. It appears that TI has simplified the structure over the yearsour chip shows the mirror directly mounted on the hinge, whereas TI's publicity shows the mirrors attached to a yoke, attached to a pair of hinges (see Figure 9). This reduction in mass probably allows the announced increase in tilt angle to 12 from 10, increasing optical efficiency.

Clearly, the DMD is a remarkable application of MEMS technology. Its digital drive system provides a switching speed that is orders of magnitude faster than competing LCD technology, and the high optical efficiency, contrast ratio and reliability are superior to both plasma and LCD displays. As a result, TI is now claiming almost 50 percent of market share in projector sales.

About the author
Dick James
is a senior technology advisor at Chipworks. He earned a Masters degree in Microelectronics and Semiconductor Devices from the University of Southampton in England, after gaining a B.Sc in Applied Chemistry from the University of Salford. He has spent over 30 years working in the process development, design, manufacturing, packaging and reverse engineering of semiconductor devices.

- Dick James
Senior technology advisor

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